XC5000 Datasheet, PDF (23/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

R
CCLK
INIT
D0-D7
1 T_IC
2 _TDC
BYTE
0
BYTE
1
T_CD 3
BYTE
2
BYTE
3
Serial Data Out
(DOUT)
RDY/BUSY
Internal INIT
LCA Filled
CS1
X6154
CCLK
Description
INIT (High) Setup time required
DIN Setup time required
DIN Hold time required
CCLK High time
CCLK Low time
CCLK Frequency
Symbol
1
T_IC
2
T_DC
3
T_CD
T_CCH
T_CCL
F_CC
Figure 16. Express Mode Programming Switching Characteristics
Min
Max
5
50
0
50
50
10
Preliminary
Units
µs
ns
ns
ns
ns
MHz
Format
Table 6 describes the XC5200 configuration data stream.
Table 7 provides details of the internal configuration data
structure.
Configuration Sequence
Figure 17 illustrates the XC5200 start-up sequence. It is
described in detail in the sections below.
Clear Internal Logic
When reprogramming the XC5200 chip, a contention-free
state must be reached before memory initialization can
begin. In this state internal control lines sequence
activities in the following order: long lines are disabled,
output drivers are forced Low, and interconnect lines are
discharged. Each of these operations requires one cycle
of the 1-MHz Initialization clock. This sequencing is
important only when reprogramming, because the
contention-free state is immediately entered when
configuring from a power-on state.
19