XC5000 Datasheet, PDF(15/48 Page) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

XC5000 Datasheet, PDF (15/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

◁

3-State Buffers

The XC5200 family has four dedicated TBUFs per CLB.

The four buffers are individually conï¬gurable through four

conï¬guration bits to operate as simple non-inverting

buffers or in 3-state mode. When in 3-state mode the

CLBâs output enable (TS) control signal drives the enable

to all four buffers (see Figure 8). Each TBUF can drive up

to two horizontal Longlines

Oscillator

The XC5200 oscillator (OSC52) divides the internal 16-

MHz clock or a user clock that is connected to the âCâ pin.

The user then has the choice of dividing by 4, 16, 64, or

256 for the âOSC1â output and dividing by 2, 8, 32, 128,

1024, 4096, 16384, or 65536 for the âOSC2â output. The

division is speciï¬ed via a âDIVIDEn_BY=xâ attribute on the

symbol, where n=1 for OSC1, or n=2 for OSC2. The

OSC5 macro is used where an internal oscillator is

required. The CK_DIV macro is applicable when a user

clock input is speciï¬ed (see Figure 9).

CLB

LC3

LC2

LC1

LC0

Horizontal

Longlines

X5706

Figure 8. XC5200 3-State Buffer

OSC5

OSC1

OSC2

OSC1

CK_DIV

CLK

OSC2

Start-Up

On start-up, all XC5200 internal ï¬ip-ï¬ops are reset. The

XC5200 devices do not support the âINIT=â attribute.

Thus, the XC5200 family has only a global reset (GR)

signal. The user can assign the pin location for the GR

signal and use it to reset asynchronously all of the ï¬ip-

ï¬ops in the design without using general routing

resources. The user can also assign a positive or negative

polarity to GR.

Boundary Scan

XC5200 devices support all the mandatory boundary-scan

instructions speciï¬ed in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that

implement the EXTEST, SAMPLE/PRELOAD, and

BYPASS instructions. The TAP can also support two

USERCODE instructions.

Boundary-scan operation is independent of individual IOB

conï¬guration and package type. All IOBs are treated as

independently controlled bidirectional pins, including any

unbonded IOBs. Retaining the bidirectional test capability

after conï¬guration provides ï¬exibility for interconnect

testing.

Also, internal signals can be captured during EXTEST by

connecting them to unbonded IOBs, or to the unused

outputs in IOBs used as unidirectional input pins. This

technique partially compensates for the lack of INTEST

support.

The public boundary-scan instructions are always

available prior to conï¬guration. After conï¬guration, the

public instructions and any USERCODE instructions are

only available if speciï¬ed in the design. While SAMPLE

and BYPASS are available during conï¬guration, it is

recommended that boundary-scan operations not be

performed during this transitory period.

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to conï¬gure the

Logic Cell Array (LCAâ¢) device, and to read back the

conï¬guration data.

All of the XC4000 boundary-scan modes are supported in

the XC5200 family. Three additional outputs for the User

representing the decoding of the corresponding state of

the boundary-scan internal state machine. For details on

boundary scan, refer to âBoundary Scan in XC4000

Devices â Application Noteâ on pages 8-45 through 8-42

of the 1994 Xilinx Programmable Logic Data Book.

Figure 9. XC5200 Oscillator Macros

▷