XC5000 Datasheet, PDF(7/48 Page) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

XC5000 Datasheet, PDF (7/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

◁

Table 3. Routing Resource Comparison

Resource

Single-length Lines

Double-length Lines

Longlines

Direct Connects

VersaRing

XC5200

yes

XC4000

â¢ The TLM process allows signiï¬cant improvements in the

routing structure. Each XC5200 VersaBlock element

has complete intra-CLB routing, the LIM, and offers four

direct routing connections to each of the four

neighboring CLBs (North, South, East, and West). Any

function generator or ï¬ip-ï¬op thus has unrestricted

connectivity to 19 other function generators or ï¬ip-

ï¬ops: three in its own CLB, and 16 in the adjacent

CLBs. These direct connects do not compete with the

general routing resources (see Table 3).

â¢ Each XC5200 3-state buffer (TBUF) can drive up to two

horizontal Longlines; each XC4000 TBUF accesses

only one horizontal Longline.

â¢ There is a special racetrack, the VersaRing, between

the outer edge of the core CLB array and the ring of

IOBs, providing signiï¬cant help in overcoming the

problems caused by early locking of I/O pins.

â¢ There are no internal pull-ups for XC5200 Longlines.

Input/Output Blocks (IOBs)

GRM

Versa-

Block

VersaRing

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

VersaRing

GRM

Versa-

Block

X4955

Figure 1. XC5200 Architectural Overview

Architectural Overview

Figure 1 presents a simpliï¬ed, conceptual overview of the

XC5200 architecture. Similar to conventional FPGAs, the

XC5200 family consists of programmable IOBs,

programmable logic blocks, and programmable

interconnect. Unlike other FPGAs, however, the logic and

local routing resources of the XC5200 family are

combined in ï¬exible VersaBlocks. General-purpose

routing connects to the VersaBlock through the General

Routing Matrix (GRM).

VersaBlock: Abundant Local Routing Plus Versatile

Logic

The basic logic element in each VersaBlock structure is

the Logic Cell, shown in Figure 2. Each LC contains a 4-

input function generator (F), a storage device (FD), and

control logic. There are ï¬ve independent inputs and three

outputs to each LC. The independence of the inputs and

outputs allows the software to maximize the resource

utilization within each LC. Each Logic Cell also contains a

direct feedthrough path that does not sacriï¬ce the use of

either the function generator or the register; this feature is

a ï¬rst for FPGAs. The storage device is conï¬gurable as

either a D ï¬ip-ï¬op or a latch. The control logic consists of

carry logic for fast implementation of arithmetic functions,

which can also be conï¬gured as a cascade chain allowing

decode of very wide input functions.

The XC5200 CLB consists of four LCs, as shown in

Figure 3. Each CLB has 20 independent inputs and 12

independent outputs. The top and bottom pairs of LCs can

be conï¬gured to implement 5-input functions. The

challenge of FPGA implementation software has always

been to maximize the usage of logic resources. The

XC5200 family addresses this issue by surrounding each

CLB with two types of local interconnect â the LIM and

direct connects. These two interconnect resources,

combined with the CLB, form the VersaBlock, represented

in Figure 4.

F2 F

CE CK CLR

X4956

Figure 2. XC5200 Logic Cell (Four LCs per CLB)

▷