XC5000 Datasheet, PDF (36/48 Pages) Xilinx, Inc – High-density family of Field-Programmable Gate Arrays

XC5200 Logic Cell Array Family
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Preliminary (v1.0)
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R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14
R2C1
R2C14
R3C1
R3C14
R4C1
R4C14
R5C1
R5C14
R6C1
R6C14
R7C1
R7C14
R8C1
R8C14
R9C1
R9C14
R10C1
R10C14
R11C1
R11C14
R12C1
R12C14
R13C1
R13C14
R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14
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KEY:
I/O Pad
R#C# _{CLB, identified by R#C# = row and column numbers}
Figure 18. XC5206 CLB-to-Pad Relationship
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