DS711 Datasheet, PDF (9/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 1: I/O Signal Description (Cont’d)
Port Signal Name
P75 M_AXI_RVALID
P76 M_AXI_RREADY
P77 M_AXI_AWLOCK
P78 M_AXI_ARLOCK
P79 M_AXI_ACLK
P80 M_AXI_ARESETN
Interface I/O
AXI_FULL/
AXI_LITE
I
AXI_FULL/
AXI_LITE
O
AXI_FULL O
AXI_FULL O
Unused AXI Signals
AXI_FULL/
AXI_LITE
I
AXI_FULL/
AXI_LITE
I
Initial
State
-
1
0
0
-
-
Description
Read valid: This signal indicates that
the required read data is available
and the read transfer can complete.
Read ready: This signal indicates
that the master can accept the read
data and response information.
Lock type: This signal provides
additional information about the
atomic characteristics of the write
transfer.
Lock type: This signal provides
additional information about the
atomic characteristics of the read
transfer.
AXI Clock - SPLB_Clk is used on AXI
side.
AXI Reset - SPLB_Rst is used on
AXI side.
Notes:
1. This signal is not used when C_SPLB_SUPPORT_BURSTS = 0 or C_EN_ERR_REGS = 0 as error registers are not enabled.
2. AXI_FULL interface refers to AXI Memory mapped interface (AXI4) enabled when C_SPLB_SUPPORT_BURSTS = 1 and
AXI_LITE interface refers to AXI4-Lite interface enable when C_SPLB_SUPPORT_BURSTS = 0.
DS711 July 25, 2012
www.xilinx.com
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Product Specification