DS711 Datasheet, PDF (8/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 1: I/O Signal Description (Cont’d)
Port Signal Name
Interface I/O
Initial
State
AXI Read Address Channel Signals
P62
M_AXI_ARID[C_M_AXI_
THREAD_ID_WIDTH-1 : 0]
AXI_FULL O
0
P63
M_AXI_ARADDR[C_M_AXI_
ADDR_WIDTH -1 : 0 ]
AXI_FULL/
AXI_LITE
O
0
P64 M_AXI_ARLEN[7 : 0]
AXI_FULL O
0
P65 M_AXI_ARSIZE[2 : 0]
AXI_FULL O
0
P66 M_AXI_ARBURST[1 : 0]
AXI_FULL O
0
P67 M_AXI_ARCACHE[3 : 0]
P68 M_AXI_ARPROT[2 : 0]
AXI_FULL O
0
AXI_FULL/
AXI_LITE
O
2
P69 M_AXI_ARVALID
AXI_FULL/
AXI_LITE
O
0
P70 M_AXI_ARREADY
P71
M_AXI_RID[C_M_AXI_
THREAD_ID_WIDTH-1 : 0]
P72
M_AXI_RDATA[C_M_AXI_
DATA_WIDTH -1 : 0]
P73 M_AXI_RRESP[1 : 0]
P74 M_AXI_RLAST
AXI_FULL/
AXI_LITE
I
-
AXI Read Data Channel Signals
AXI_FULL I
-
AXI_FULL/
AXI_LITE
I
-
AXI_FULL/
AXI_LITE
I
-
AXI_FULL/
AXI_LITE
I
-
Description
Read address ID: This signal is the
identification tag for the read address
group of signals.
Read address: The read address bus
gives the initial address of a read
burst transaction.
Burst length: The burst length gives
the exact number of transfers in a
read burst.
Burst size: This signal indicates the
size of each transfer in the read
burst.
Burst type: The burst type, coupled
with the size information, details how
the address for each read transfer
within the burst is calculated.
Cache type: This signal provides
additional information about the
cacheable characteristics of the read
transfer.
Protection type: This signal provides
protection unit information for the
read transaction. The default value is
normal non secure data access.
Read address valid: This signal
indicates, when HIGH, that the read
address and control information is
valid and remains stable until the
address acknowledgement signal,
ARREDY, is high.
Read address ready: This signal
indicates that the slave is ready to
accept an address and associated
control signals.
Read ID tag: This signal is the ID tag
of the read data group of signals. The
RID value is generated by the slave
and must match the ARID value of
the read transaction to which it is
responding.
Read data bus
Read response: This signal indicates
the status of the read transfer.
Read last: This signal indicates the
last transfer in a read burst.
DS711 July 25, 2012
www.xilinx.com
8
Product Specification