DS711 Datasheet, PDF (40/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
The PLBV46 to AXI Bridge resource utilization benchmarks for many parameter combinations are measured with
the Spartan®-6 FPGA as the target device are shown in Table 18.
Table 18: Performance and Resource Utilization Benchmarks Spartan-6 FPGA (XC6SLX100t-FGG900-2)
Parameter Values (other parameters at default value)
Device Resources
Perfor
mance
1
32
32
0
NA NA NA
NA
1
0
69
228 210 100
0
32
64
0
NA NA NA
1
0
0
88
292 212 100
0
32 128
0
NA NA NA
1
0
0
94
292 198 100
0
32
32
1
0
0
0
1
1
0
202 545 546 100
0
32
32
1
0
1
0
2
1
0
223 661 655 100
0
32
32
1
1
1
0
3
1
0
232 691 688 100
0
64
64
1
1
1
0
3
1
0
299 800 786 100
0
32 128
1
1
1
1
4
1
0
367 1040 1264 100
0
64 128
1
1
1
1
4
1
0
490 1172 1407 100
0
64 128
1
1
1
1
1
0
0
498 1172 1351 100
0
64 128
1
1
1
0
4
1
2
204 512 664 100
0
64 128
1
1
1
0
1
1
4
225 512 705 100
Read Latency and PLB Bandwidth Utilization
The core is configured for best possible configuration for calculation of latency and bandwidth utilization.
The read latency from address valid (SPLB_PAValid) to first data beat (Sl_rdDAck) of PLBV46 to AXI Bridge is
as shown in Table 19.
Table 19: Read latency in PLB clocks
C_SPLB_SUPPORT_BURSTS
0
0
1
1
C_SPLB_P2P
1
0
1
0
Read Latency
3 clocks
4 clocks
5 clocks
6 clocks
DS711 July 25, 2012
www.xilinx.com
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Product Specification