DS711 Datasheet, PDF (13/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 2: Design Parameters (Cont’d)
Generic Feature/Description
G43
No byte swap base address for
address region 2
G44
No byte swap high address for
address region 2
G45
No byte swap base address for
address region 3
G46
No byte swap high address for
address region 3
G47
No byte swap base address for
address region 4
G48
No byte swap high address for
address region 4
Parameter Name
C_NBS_RNG2_BASEADDR
C_NBS_RNG2_HIGHADDR
C_NBS_RNG3_BASEADDR
C_NBS_RNG3_HIGHADDR
C_NBS_RNG4_BASEADDR
C_NBS_RNG4_HIGHADDR
Allowable
Values
Valid address⁽¹⁹⁾
Valid address⁽¹⁹⁾
Valid address⁽¹⁹⁾
Valid address⁽¹⁹⁾
Valid address⁽¹⁹⁾
Valid address⁽¹⁹⁾
Default
Values
None
None
None
None
None
None
VHDL
Type
std_logic
_vector
std_logic
_vector
std_logic
_vector
std_logic
_vector
std_logic
_vector
std_logic
_vector
1. When C_SPLB_P2P is set to 1, the PLBV46 to AXI Bridge does not require an address range specified by
C_SPLB_RNGx_BASEADDR and C_SPLB_RNGx_HIGHADDR. Also C_SPLB_RNGS_OFFSET is not valid.
2. This can be enabled only when C_SPLB_SUPPORT_BURSTS = 1. When C_SPLB_SUPPORT_CACHELINE is set to zero, 4-word
and/or 8-word cache line transactions are not supported on PLB. It is recommended to set this to 1 when PLB master generates
cache line transfers.
3. Four sets of address ranges can be specified for the bridge so that different protection and cache encoding can be selected for
different address ranges. The range specified by the various base addresses and corresponding high addresses must comprise a
complete, contiguous power of two range such that range = 2ⁿ, and the n least significant bits of the base address must be zero. If
an address range needs to support 16 word burst transactions, the base address for this address range must be aligned to a
64-byte address.
4. No default value is specified to ensure that the actual value is set, that is, if the value is not set, a compiler error is generated. High
address - base address must be a power of 2.
5. Only valid if C_SPLB_P2P = 0 and should be word aligned. C_SPLB_RNGx_BASEADDR+C_SPLB_OFFSET represents the base
AXI address that the PLB is allowed to access for the range x (x varies from 1 to 4). For example, if C_SPLB_OFFSET is
0x00000000, C_SPLB_RNG1_BASEADDR represents the physical address of AXI. C_SPLB_RNG1_BASEADDR value of
0x00000000 will go to physical address 0x00000000. A value of 0x02000000 will go to physical address 0x02000000. If you
increase the C_SPLB_OFFSET to 0x03000000, a C_SPLB_RNG1_BASEADDR value of 0x00000000 will go to physical address
0x03000000, a C_SPLB_RNG1_BASEADDR value of 0x02000000 will go to physical address 0x05000000.
6. C_SPLB_RNGx_HIGHADDR+C_SPLB_OFFSET represents the high AXI address that the PLB is allowed to access for the range
x.
7. The selected protection level is used for the entire range of bridge address and for all the AXI transactions. M_AXI_ARPROT[0],
M_AXI_AWPROT[0], M_AXI_ARPROT[2], M_AXI_AWPROT[2] M_AXI_ARPROT[3] and M_AXI_AWPROT[3] bits are set to zero.
8. The selected transaction attributes are used for the entire range of a bridge address and for all the AXI transactions. Read allocate
and Write allocate are set to zero.
9. The user must set these values only when C_EN_ERR_REGS = 1. The C_SPLB_BRIDGE_BASEADDR must be a multiple of the
range, where the range is C_SPLB_BRIDGE_HIGHADDR - C_SPLB_BRIDGE_BASEADDR + 1.
10. This parameter is not used when C_SPLB_SUPPORT_BURSTS = 0, as the AXI interface is AXI4-Lite and the number of
outstanding transfers is always 1.
11. SPLB_SAValid is used only when C_M_AXI_SUPPORTS_THREADS = 1.
12. C_M_AXI_DATA_WIDTH value will be set the same as C_SPLB_NATIVE_DWIDTH. C_M_AXI_DATA_WIDTH is set to 32 when
C_SPLB_SUPPORT_BURSTS = 0 as AXI4-Lite interface is used on AXI side.
13. This parameter is used by Interconnect and updated automatically. When C_SPLB_NATIVE_DWIDTH is 64,
C_SUPPORTS_NARROW_BURST is set to 1. When C_SPLB_NATIVE_DWIDTH is 32, C_SUPPORTS_NARROW_BURST is set
to 0 as narrow transfers are not generated.
14. This parameter is used by Interconnect and updated automatically. See Table 7 and Outstanding Requests on AXI for more details.
15. When C_SPLB_SUPPORT_BURSTS = 1, C_M_AXI_PROTOCOL is updated automatically to axi4 and when
C_SPLB_SUPPORT_BURSTS = 0, C_M_AXI_PROTOCOL is updated automatically to axi4lite.
16. When C_SPLB_P2P = 1, and C_EN_ERR_REGS = 1 all the PLB requests other than the register space address range
(C_SPLB_BRIDGE_BASEADDR to C_SPLB_BRIDGE_BASEADDR + 0xF) is translated to AXI. When C_SPLB_P2P = 1, and
C_EN_ERR_REGS = 0 all the PLB requests are translated to AXI.
17. C_EN_ERR_REGS is set to 0, when C_SPLB_SUPPORT_BURSTS = 0 as error registers are not required.
DS711 July 25, 2012
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Product Specification