DS711 Datasheet, PDF (19/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Read and Write Ordering
When a read followed by a write (or vice versa) is issued to the same address from the PLB, the PLBV46 to AXI
Bridge implements an address check against the outstanding transactions and ensures the transactions are issued
and completed in order.
When a write followed by write (or read followed by read) to the same address is issued from PLB, the PLBV46 to
AXI Bridge does not implement the address check against the two addresses and issues these transactions with
different ID values and assumes that the transactions will complete in order.
AXI Response Signaling
EXOKAY is considered as OKAY.
Protection Unit Support
Protection unit support is limited in PLBV46 to AXI Bridge. Privileged and instruction accesses are not supported.
All the transactions are normal data accesses. Either secure or non-secure is selected during configuration by the
parameter C_SPLB_RNGx_NONSEC_SEC. When this is set to 0, M_AXI_ARPROT[1] and M_AXI_AWPROT[1] are
set to 0 for address range x (x varies from 1 to 4). When this is set to 1, M_AXI_ARPROT[1] & M_AXI_AWPROT[1]
are set to 1.
When C_SPLB_P2P = 1, M_AXI_ARPROT[1] and M_AXI_AWPROT[1] are set to ‘1’ and the remaining bits are set to
zero.
Cache Support
The bufferable and cacheable transaction attributes of AXI transfers are selected by the parameter
C_SPLB_RNGx_CACHEABLE_BUFFERABLE. Assignment of M_AXI_AWCACHE and M_AXI_ARCACHE for
different values of C_SPLB_RNGx_CACHEABLE_BUFFERABLE is shown in Table 6. When C_SPLB_P2P = 1,
M_AXI_ARCACHE[3:0] and M_AXI_AWCACHE[3:0] are set to zeroes for all the AXI requests.
Table 6: Assignment of M_AXI_AWCACHE and M_AXI_ARCACHE
C_SPLB_RNGx_CACHEABLE_BUFFERABLE
M_AXI_AWCACHE[3:0]
0
“0000”
1
“0001”
2
“0010”
3
“0011”
M_AXI_ARCACHE[3:0]
“0000”
“0001”
“0010”
“0011”
Bridge Error Conditions
An error on AXI results with the response of SLVERR or DECERR. As the bridge supports posted writes and out-of-
order reads, these errors cannot be sent on the PLB. For this reason the PLBV46 to AXI Bridge implements the
optional Slave Error Address Register (SEAR) and Slave Error Status Register (SESR). The SESR/SEAR registers are
accessible from the PLB and are used for system integration and debug or error event logging by a user application.
These registers capture the PLB request status and qualifiers as well as the target address when a read or write
transaction generates an error on the AXI side. An interrupt signal is driven by the PLB slave to the system interrupt
controller to report these errors, when interrupts are enabled by using the Device Global Interrupt Enable Register
(DGIE) and Device Interrupt Enable Register (DIER). When both write and read requests on AXI generates errors,
a write error has more priority than a read error, so the status qualifiers shows the information of write request that
caused the error.
DS711 July 25, 2012
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Product Specification