DS711 Datasheet, PDF (20/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
When C_SPLB_P2P = 0, a BAR (Base Address Roll over) error is generated when the PLB address overruns the
C_SPLB_RNGx_HIGHADDR for range x. When C_SPLB_P2P = 1, a BAR error is generated when the PLB address
overruns 0xFFFFFFFF. A BAR error is not applicable for single transfers when C_SPLB_SUPPORT_BURSTS = 0.
It is the user’s responsibility not to issue burst transfers that cross the PLBV46 to AXI bridge’s high address. During
such transfers, the PLB address is not acknowledged by the bridge and PLB_MTimeout is issued by the arbiter after
16 clock cycles. An edge-sensitive interrupt is generated by the bridge if C_EN_ERR_REGS is 1 and interrupts are
enabled. The SESR register shows the status of the transfer that caused a BAR error and the SEAR shows the address
of the transfer.
Bridge Time Out Condition
Data phase time out is not implemented inside the bridge. When a request is issued from the PLB, the bridge
translates this request into corresponding AXI transfer and requests on AXI. If this request is not responded by AXI,
the PLBV46 to AXI bridge and hence PLB waits indefinitely. There is no mechanism implemented inside the
PLBV46 to AXI bridge to come out of this kind of situation. It is assumed that AXI responds to all of the AXI
requests.
4 KB Crossing
As per the AXI specification, bursts must not cross 4 KB boundaries to prevent them from crossing boundaries
between slaves and to limit the size of the address incrementer required within slaves. PLBV46 to AXI Bridge takes
care of this inside the bridge by splitting the PLB burst transfer into two requests when the PLB issues a burst
transfer that crossed 4KB boundary.
Outstanding Requests on AXI
The number of outstanding write /read requests on AXI can be more than 1 when C_SPLB_SUPPORT_BURSTS =
1 and C_M_AXI_SUPPORTS_THREADS = 1. The read/write transfers that are requested on SPLB_SAValid are
requested on AXI with a different ID and the reordering depth is 2. Therefore, the outstanding read/write request
are 2. When a 4 KB crossing is detected in a PLB word or double-word burst in both primary and secondary
transfers, outstanding write/read requests are 4 (2 for the requests on SPLB_PAValid and 2 for the requests on
SPLB_SAValid).
The following Table 7 shows more details on the number of outstanding requests that are generated on AXI
depending on the generic combinations.
Table 7: Outstanding write/read requests
C_SPLB_SUPPORT_ C_M_AXI_SUPPORT_T
BURSTS
HREADS
0
NA
1
0
1
1
C_INTERCONNECT_M_AXI_
READ_ISSUING/C_INTERCONNECT_M_AXI_WRITE_ISSUING
1
2
4
AXI4-Lite Operation
When C_SPLB_SUPPORT_BURST = 0, only single transfers are supported on the PLB and the AXI4-Lite interface is
used on AXI side. For all the other PLB transfers (Example: line and burst transfers), the PLBV46 to AXI bridge does
not respond and PLB_MTimeout is issued by the arbiter after 16 clock cycles.
DS711 July 25, 2012
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Product Specification