DS711 Datasheet, PDF (4/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Read Buffer
The Read Buffer stores the read data from the AXI Master module during out-of-order read transactions. This is
enabled when C_M_AXI_SUPPORTS_THREADS = 1. When enabled, the address pipelining depth on PLB is two
and outstanding addresses issued on AXI are two. The read buffer is needed when these back-to-back read transfers
on AXI are responded in out-of-order by AXI slaves. The Read Buffer contains a FIFO of width 32/64-bit and depth
of 16. The width of the FIFO is directly dependent on C_SPLB_NATIVE_DWIDTH. The Read Buffer passes the read
data to the PLBv46 Slave module.
Bridge Control Logic
The PLBV46 to AXI Bridge needs to split a burst transfer that crosses a 4 K byte boundary as required by AXI. The
Bridge Control Logic module generates the 4 KB crossing control signals and provides the length and address sig-
nals to the AXI Master module. This module is not used when C_SPLB_SUPPORT_BURSTS = 0 as AXI4-Lite inter-
face is used on AXI side.
Register and Interrupt
The Register and Interrupt module contains the bridge registers and generates interrupts. This is enabled when
both parameters C_EN_ERR_REGS and C_SPLB_SUPPORT_BURSTS are set to 1. These registers capture the PLB
request status and qualifiers as well as the target address when a write or read transaction generates an error on the
AXI side. An interrupt is generated to report these errors. See Register Descriptions for more details.
The register accesses are always 32-bit and only PLB single transfers are acknowledged in the register address
space. The slave size is always 32-bit even when C_SPLB_NATIVE_DWIDTH is 64. This module is not imple-
mented when C_SPLB_SUPPORT_BURSTS = 0 and the error information is sent on Sl_MRdErr and Sl_MWrErr
signals. Also the interrupt signal is not used.
AXI Master
The AXI Master module provides a bidirectional AXI master interface on the AXI. This interface can be AXI
memory-mapped interface (AXI4) or AXI4-Lite interface (control interface) depending on the parameter
C_SPLB_SUPPORT_BURSTS. When C_SPLB_SUPPORT_BURST = 0, only single transfers on PLB are supported
and the AXI4-Lite interface is used on the AXI side. When C_SPLB_SUPPORT_BURSTS = 1, the AXI4 interface is
used on AXI. The AXI data bus width can be 32 or 64-bits in theAXI4 interface and always fixed at 32 when AXI4-
Lite interface is used. This module receives read data from AXI and transmits to either read buffer when the read
buffer is enabled or to PLBv46 Slave module when the read buffer is disabled. During write transfers the write data
is received from the write buffer. Depending on the design parameters, the AXI Master module controls the sup-
ported limited cache encoding (cacheable/bufferable) and limited protection encoding (secure/non-secure) sig-
nals.
DS711 July 25, 2012
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