DS711 Datasheet, PDF (18/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Memory Mapping
The AXI memory map and the PLB memory map are one single complete 32-bit (4 GB) memory space. The PLBV46
slave module in the bridge does not modify the address for AXI; hence, the address that is presented on the AXI is
exactly as received on the PLB when C_SPLB_RNGS_OFFSET is set to “0x00000000”.
Address Decoding
Address decoding is required in a shared bus interconnect scheme when C_SPLB_P2P = 0. In a Point to Point
configuration (C_SPLB_P2P = 1), there is only one PLB master that communicates with the PLBV46 to AXI Bridge.
So the bridge responds to all addresses regardless of the address and the PLB Slave module might be able to reduce
resource utilization by eliminating the address decode function and modifying interface behavior to allow for a
reduction in latency.
In a shared bus topology (C_SPLB_P2P = 0), the PLBV46 to AXI Bridge decodes the address presented on the
address bus.
Relationships Between the Write AXI Channels
As the relationship between the address, write data, and write response channels is flexible on AXI, the PLBV46 to
AXI bridge issues the write address independent of write data and vice versa.
Read Ordering
When C_SPLB_SUPPORT_BURSTS = 1 and C_M_AXI_SUPPORTS_THREADS = 1, the PLBV46 to AXI Bridge
issues the reads on AXI with different read transfer ID values. The transfers that are requested on SPLB_SAValid
are sent on AXI with different M_AXI_ARID. The read reordering depth is 2 and read data interleaving is supported
among these transfers. The out-of-order read completion on AXI is supported by storing the read data. The AXI
read slave error is not sent on PLB (on Sl_MRdErr) for the reads that are completed out of order on AXI.
When C_M_AXI_SUPPORTS_THREADS is set to 0, the AXI master module issues the reads with same read
transfer ID values so that they are received in order.
When C_SPLB_SUPPORT_BURSTS = 0, only PLB single read transfers are supported and IDs are not used.
Write Ordering
When C_SPLB_SUPPORT_BURSTS = 1 and C_M_AXI_SUPPORTS_THREADS = 1, the PLBV46 to AXI Bridge
issues write transactions with different transfer ID values where the data ordering depth is 2 and allows the write
responses in out-of-order. The transfers that are requested on SPLB_SAValid are sent on AXI with different
M_AXI_WID. However the bridge issues the data of write transaction in the same order in which it issues the
transaction addresses as the PLB sends the write data in order.
When C_M_AXI_SUPPORTS_THREADS is set to 0, the AXI master module issues the writes with same write
transfer ID values so that they are received in order.
The write error response is not sent on PLB (on Sl_MWrErr) as the write data acknowledge is sent on PLB before
the data is sent on AXI. The user has to enable the error registers (set C_EN_ERR_REGS = 1) for such errors.
When C_SPLB_SUPPORT_BURSTS = 0, only PLB single write transfers are supported and IDs are not used.
DS711 July 25, 2012
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