DS711 Datasheet, PDF (5/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
I/O Signals
Table 1 shows the Input/Output (I/O) signals of the PLBV46 to AXI Bridge.
Table 1: I/O Signal Description
Port Signal Name
P1 SPLB_Clk
P2 SPLB_Rst
Interface I/O
PLB System Signals
System
I
System
I
Initial
State
-
-
P3 Interrupt⁽¹⁾
System
O
0
PLB Interface Signals
P4 SPLB_ABus[0:C_SPLB_AWIDTH -1]
PLB
I
-
P5 SPLB_PAValid
PLB
I
-
P6
SPLB_masterID[0:C_SPLB_MID_
WIDTH - 1]
PLB
I
-
P7 SPLB_RNW
PLB
I
-
P8 SPLB_BE[0 : (C_SPLB_DWIDTH/8) - 1]
PLB
I
-
P9 SPLB_size[0 : 3]
PLB
I
-
P10 SPLB_type[0 : 2]
PLB
I
-
P11 SPLB_wrDBus[0 : C_SPLB_DWIDTH - 1]
PLB
I
-
P12 SPLB_SAValid
PLB
I
-
P13 SPLB_MSize[0 : 1]
PLB
I
-
PLB Slave Interface Signals
P14 Sl_addrAck
PLB
O
0
P15 Sl_SSize[0 : 1]
PLB
O
0
P16 Sl_wait
PLB
O
0
P17 Sl_rearbitrate
PLB
O
0
P18 Sl_wrDAck
PLB
O
0
P19 Sl_wrComp
PLB
O
0
P20 Sl_rdDBus[0 : C_SPLB_DWIDTH - 1]
PLB
O
0
P21 Sl_rdDAck
PLB
O
0
P22 Sl_rdComp
PLB
O
0
P23 Sl_MBusy[0 : C_SPLB_NUM_MASTERS - 1] PLB
O
0
P24 Sl_MRdErr[0 : C_SPLB_NUM_MASTERS - 1] PLB
O
0
P25 Sl_MWrErr[0 : C_SPLB_NUM_MASTERS - 1] PLB
O
0
P26 Sl_rdWdAddr[0 : 3]
PLB
O
0
P27 Sl_wrBTerm
PLB
O
0
P28 Sl_rdBTerm
PLB
O
0
Description
PLB clock
PLB reset, active-High
Bridge Interrupt (Edge sensitive,
rising)
PLB address bus
PLB primary address valid
PLB current master identifier
PLB read not write
PLB byte enables
PLB size of requested transfer
PLB transfer type
PLB write data bus
PLB secondary address valid
PLB data bus width indicator
Slave address acknowledge
Slave data bus size
Slave wait
Slave bus rearbitrate
Slave write data acknowledge
Slave write transfer complete
Slave read data bus
Slave read data acknowledge
Slave read transfer complete
Slave busy
Slave read error
Slave write error
Slave read word address
Slave terminate write burst transfer
Slave terminate read burst transfer
DS711 July 25, 2012
www.xilinx.com
5
Product Specification