DS711 Datasheet, PDF (16/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 3: Parameter-I/O Signal Dependencies (Cont’d)
Generic
or Port
Name
Affects Depends Relationship Description
P20
Sl_rdDBus[0 : C_SPLB_DWIDTH - 1]
-
G3
Width of the Sl_rdDBus varies
according to C_SPLB_DWIDTH
P23
Sl_MBusy[0 : C_SPLB_NUM_MASTERS - 1]
-
G7
Width of the Sl_MBusy varies
according to
C_SPLB_NUM_MASTERS.
P24
Sl_MWrErr[0 : C_SPLB_NUM_MASTERS - 1]
-
G7
Width of the Sl_MWrErr varies
according to
C_SPLB_NUM_MASTERS.
P25
Sl_MRdErr[0 : C_SPLB_NUM_MASTERS - 1]
-
G7
Width of the Sl_MRdErr varies
according to
C_SPLB_NUM_MASTERS
P53
M_AXI_WDATA[C_M_AXI_DATA_WIDTH -1 : 0]
-
Width of the M_AXI_WDATA varies
G33
according to
C_M_AXI_DATA_WIDTH
P54
M_AXI_WSTRB[(C_M_AXI_DATA_WIDTH/8) -1 : 0] -
Width of the M_AXI_WSTRB varies
G33
according to
C_M_AXI_DATA_WIDTH.
P72
M_AXI_RDATA[C_M_AXI_DATA_WIDTH -1 : 0]
-
Width of the M_AXI_RDATA varies
G33
according to
C_M_AXI_DATA_WIDTH.
Design Details
Clocking
The PLBV46 to AXI Bridge is a synchronous design and uses the PLB clock at both PLB and AXI interfaces.
Reset
SPLB_Rst is synchronous reset input that resets the bridge upon assertion. The SPLB_Rst is also used to reset AXI
interface.
Byte Invariance
AXI is little endian and PLB is big endian. The PLBV46 to AXI Bridge maintains byte invariance, or using Xilinx IP
terminology, byte addressing integrity is maintained for both 32 and 64-bit width data in the bridge design when
C_EN_BYTE_SWAP = 1. This means that a 32/64-bit data from any address on the PLBV46 bus has the bytes
swapped in traversing the bridge so that byte data of byte lanes of the same numerical address offsets yields the
same byte data when read from the little endian AXI side or by a remote master on the big endian PLB side. For byte
transactions, any byte addressed data read from the AXI side or the PLB side yields the same byte of data. Write
strobe signals from the AXI master port are similarly swapped. Byte and strobe swapping are shown in Figure 2 for
32-bit data width on PLB and AXI (C_SPLB_NATIVE_DWIDTH = 32). When C_EN_BYTE_SWAP = 0, no bytes are
swapped.
DS711 July 25, 2012
www.xilinx.com
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Product Specification