DS711 Datasheet, PDF (12/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 2: Design Parameters (Cont’d)
Generic Feature/Description
Parameter Name
Allowable
Values
AXI Parameters
G30
AXI Identification tag width
C_M_AXI_THREAD_ID_
WIDTH⁽¹⁰⁾
1-2
Indicates generation of more than
one outstanding transfers
G31
0 = Master generates one master C_M_AXI_SUPPORTS_
ID
THREADS^(10)(11)
0-1
1= Master generates two master
IDs
G32
AXI most significant address bus
width
C_M_AXI_ADDR_WIDTH
32
G33
AXI data bus width
C_M_AXI_DATA_WIDTH
32, 64
EDK Tool Parameters
G34
Supports narrow bursts
C_SUPPORTS_NARROW_
BURST
0-1
Maximum number of data-active
G35
read transactions generated. This
is set as the
READ_ACCEPTANCE parameter
C_INTERCONNECT_M_AXI_
READ_ISSUING
1-4
on the interconnect.
Maximum number of data-active
G36
write transactions generated. This
is set as the
WRITE_ACCEPTANCE
C_INTERCONNECT_M_AXI_
WRITE_ISSUING
1-4
parameter on the interconnect.
G37
AXI interface type
C_M_AXI_PROTOCOL⁽¹⁵⁾
axi4,axi4lite
PLBV46 to AXI Bridge specific Parameters
Enable Error Registers for error
information and generating
interrupt
G38
0 = No error registers are
implemented
C_EN_ERR_REGS^(16)(17)
0-1
1 = Error registers are
implemented
Enable byte swapping from PLB to
AXI
G39
0 = No swapping is performed
C_EN_BYTE_SWAP
0-1
1 = Byte swapping is performed
Number of no byte swap address
G40
regions when
C_NBS_NUM_ADDR_RNGS 0-4⁽¹⁸⁾
C_EN_BYTE_SWAP is 1.
G41
No byte swap base address for
address region 1
C_NBS_RNG1_BASEADDR
Valid address⁽¹⁹⁾
G42
No byte swap high address for
address region 1
C_NBS_RNG1_HIGHADDR
Valid address¹⁹⁾
Default
Values
1
0
32
32⁽¹²⁾
0⁽¹³⁾
2⁽¹⁴⁾
2⁽¹⁴⁾
axi4
0
0
0
None
None
VHDL
Type
integer
integer
integer
integer
integer
integer
integer
string
integer
integer
integer
std_logic
_vector
std_logic
_vector
DS711 July 25, 2012
www.xilinx.com
12
Product Specification