DS711 Datasheet, PDF (3/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Functional Description
Overview
The PLBV46 to AXI Bridge translates PLB transactions into AXI transactions. The bridge functions as a slave on the
PLB and as a master on the AXI.
The PLBV46 to AXI Bridge block diagram is shown in Figure 1 and described in following sections.
X-Ref Target - Figure 1
PLBv46
Write
Buffer
PLBv46
Slave
Read
Buffer
Bridge
Control
Logic
AXI
Master
AXI4
AXI Full/AXI Lite
AXI4-Lite
Interrupt
Register
and
Interrupt
Legend:
Indicates optional.
Figure 1: PLBV46 to AXI Bridge Block Diagram
DS711_01
PLBv46 Slave
The PLBv46 Slave module provides a bidirectional slave interface to the PLB. The PLB data bus width can be con-
figured by setting the parameters as shown in Table 2. This module decodes the address for the bridge registers and
for the slaves on the AXI when C_SPLB_P2P = 0. This module also implements the logic to detect if overlapping
write and read requests are issued from the PLB. As AXI has independent read and write channels, these requests
are issued in such a way that the data coherency is maintained.
Write Buffer
The Write Buffer stores the write data from the PLBv46 Slave module during the posted write transactions. This is
enabled when C_SPLB_SUPPORT_BURSTS = 1. The write buffer is implemented in the bridge to free up the master
transactions to other cores that might be on the PLB. The Write Buffer contains a First In First Out (FIFO) of width
32/64-bit and depth of 16. The width of the FIFO is directly dependent on C_SPLB_NATIVE_DWIDTH. The Write
Buffer passes the write data to the AXI Master module.
DS711 July 25, 2012
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