DS711 Datasheet, PDF (22/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 9: Slave Error Status Register (SESR) Bit Definitions
Bit(s) Name
Core
Access
Reset
Value
Description
0-20 Reserved
N/A
0
Reserved
21-23
Size
R/W⁽¹⁾
“0000”
PLB Size:
This value reflects the SPLB_size qualifier at the time of error capture.See
IBM PLB Specification for SPLB_size description.
24-27
MID
R/W⁽¹⁾
“0000”
PLB Master ID:
This value reflects the SPLB_masterID qualifier at the time of error capture.
See IBM PLB Specification for SPLB_masterID description.
28
RNW
R/W⁽¹⁾
29
BAR
R/W⁽¹⁾
PLB RNW:
This bit reflects the state of the SPLB_RNW signal at the time of the error
‘0’
capture.
‘0’ = Write command.
‘1’ = Read command.
BAR Error:⁽²⁾⁽³⁾
This bit is asserted when a PLB address overruns the address range of the
‘0’
bridge.
‘0’ = No BAR Error asserted.
‘1’ = BAR Error asserted.
30 DECERR R/W⁽¹⁾
Decode Error:
This bit is asserted when a decode error (DECERR) is received from the AXI
‘0’
interconnect component. This indicates that there is no slave at the
transaction address.
‘0’ = No Decode Error asserted.
‘1’ = Decode Error asserted.
31 SLVERR R/W⁽¹⁾
Slave Error:
This bit is asserted whenever a slave error (SLVERR) is received from the AXI
‘0’
Slave. This indicates that the access has reached the AXI slave successfully,
but the slave wishes to return an error condition.
‘0’ = No Slave Error asserted.
‘1’ = Slave Error asserted.
Notes:
1. This register is cleared by the user application through a system reset or a write to the SESR address with a data value of
0xA0000000.
2. During a BAR error, the PLBV46 to AXI bridge does not send address acknowledge due to which PLB_MTimeout is asserted by
arbiter. This transfer is not sent on AXI.
3. A BAR error is applicable for only burst transfers. This bit is always zero when C_SPLB_SUPPORT_BURSTS = 0.
X-Ref Target - Figure 4
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Figure 4: Slave Error Address Register (SEAR)
DS711 July 25, 2012
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Product Specification