DS711 Datasheet, PDF (14/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
18. Four sets of address ranges can be specified for the no byte swap address regions in the given PLB address ranges. This
parameter is used when C_EN_BYTE_SWAP is ‘1’ only and is ignored when C_EN_BYTE_SWAP is ‘0’. By default the value of the
parameter is ‘0’.This parameter is required for the AXI slaves which have mixed address space for registers and memory.The byte
invariance is ignored for the accesses in these address regions.
19. These address ranges are valid based on the C_NBS_NUM_ADDR_RNGS and when C_EN_BYTE_SWAP is ‘1’. The AXI slave
register address spaces must be provided in these no byte swap address regions. There will not be byte swapping/byte in variance
for these register addresses. Narrow transfers are not allowed in these no byte swap address regions.
Allowable Parameter Combinations
When C_EN_ERR_REGS = 1 and C_SPLB_SUPPORT_BURSTS = 1, C_SPLB_BRIDGE_BASEADDR and
C_SPLB_BRIDGE_HIGHADDR must be specified. The address range specified by C_SPLB_BRIDGE_BASEADDR
and C_SPLB_BRIDGE_HIGHADDR must be a power of 2, and must be at least 0xF in size.
For example, if C_SPLB_BRIDGE_BASEADDR = 0xE0000000, C_SPLB_BRIDGE_HIGHADDR must be at least =
0xE000000F.
Parameter - I/O Signal Dependencies
The dependencies between the PLBV46 to AXI Bridge core design parameters and I/O signals are described in
Table 3. In addition, when certain features are parameterized out of the design, the related logic is no longer a part
of the design. The unused input signals and related output signals are set to a specified value.
Table 3: Parameter-I/O Signal Dependencies
Generic
or Port
Name
Affects Depends Relationship Description
Design Parameters
G3
C_SPLB_DWIDTH
G3
C_SPLB_DWIDTH
G4
C_SPLB_NATIVE_DWIDTH
G5
C_SPLB_P2P
G5
C_SPLB_P2P
G6
C_SPLB_MID_WIDTH
G7
C_SPLB_NUM_MASTERS
G4
P8, P11,
P20
-
G8
G10 to
G27
P16,
P17
P6
G9
P23,
P24,
-
P25
C_SPLB_DWIDTH should be
greater than or equal to
C_SPLB_NATIVE_DWIDTH.
Affects the number of bits of read
and write data bus and byte enables
The allowed value of
C_SPLB_NATIVE_DWIDTH is 32
when
C_SPLB_SUPPORT_BURSTS = 0.
When C_SPLB_P2P = 1, as
address decoding is not needed the
generics related to address ranges
are not used.
When C_SPLB_P2P = 1, Sl_wait is
driven when the bridge is busy.
When C_SPLB_P2P = 0,
Sl_rearbitrate is driven when the
bridge is busy.
This value is calculated as:
log₂(C_SPLB_NUM_MASTERS)
with a minimum value of 1.
Affects the width of the Sl_MBusy,
Sl_MWrErr and Sl_MRdErr
DS711 July 25, 2012
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Product Specification