DS711 Datasheet, PDF (1/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

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DS711 July 25, 2012
LogiCORE IP PLBV46 to AXI
Bridge (v2.01.a)
Product Specification
Introduction
The Processor Local Bus (PLB v4.6) to Advanced Micro-
controller Bus Architecture (AMBA^®) Advanced eXten-
sible Interface (AXI) Bridge translates PLBV46
transactions into AXI4 transactions. It functions as a
slave on the PLBV46 and as a master on the AXI4. The
PLBV46 to AXI Bridge main use model is to connect the
AXI slaves with PLB masters.
Features
The Xilinx® PLBV46 to AXI Bridge is a soft Intellectual
Property (IP) core with the following features:
PLBV46 Slave Interface
• Connects as a 32/64-bit slave on PLB v4.6 buses of
32, 64 or 128 bits
• Supports 1:1 (PLB:AXI) synchronous clock ratio
• Supports access by 32, 64-bit PLB masters
• Supports Xilinx simplified PLBv46 protocol
• Single transfers of 1 to 8 bytes
• Optional line transfers of 4 and 8 words
• Optional Fixed length burst transfers of 2 to 16
data beats of words and double words
• Supports optional two levels of address pipelining
• Supports split bus architecture (simultaneous read
and write operations)
• Supports optional PLB status/interrupt registers
and generates interrupts
• Supports optional low latency PLB Point-to-Point
topology
• Supports 1 to 4 address ranges with selectable
cache encoding and protection unit support
AXI Master Interface
• Connects as a 32/64-bit master on 32/64-bit AXI4
interface
• Connects as a 32-bit master on 32-bit AXI4-Lite
interface
• Support burst transfers of 1 to 32 words or 1 to 16
double words of INCR type and burst transfers of
4 and 8 only of WRAP type
• Supports optional generation of two outstanding
addresses and supports out-of-order read
transaction completion and out-of-order write
transaction completion
• Supports optional limited cache encoding
(cacheable/bufferable) and limited protection unit
support (secure/non-secure)
LogiCORE IP Facts Table
Supported
Device Family⁽¹⁾
Core Specifics
Zynq™-7000⁽²⁾, Virtex®-7⁽³⁾, Kintex™-7^(3),
Artix™-7⁽³⁾,
Virtex-6⁽⁴⁾ Spartan®-6⁽⁵⁾
Supported User
Interfaces
PLBV46, AXI4/AXI4-Lite
Resources
See Table 14 through Table 18.
Provided with Core
Design Files
VHDL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
None
Simulation
Model
None
Supported S/W
Driver
N/A
Tested Design Flows⁽⁶⁾
Design Entry
Xilinx Platform Studio (XPS)
Vivado™ Design Suite⁽⁷⁾
Simulation
Mentor Graphics ModelSim
Synthesis Tools
Xilinx Synthesis Technology (XST)
Vivado Synthesis
Support
Provided by Xilinx@ www.xilinx.com/support
Notes:
1. For a complete list of supported derivative devices, see
Embedded Edition Derivative Device Support.
2. Supported in ISE Design Suite implementations only.
3. For more information, see DS180, 7 Series FPGAs
Overview.
4. For more information, see DS150, Virtex-6 Family Overview.
5. For more information, see DS160, Spartan-6 Family
Overview.
6. For the supported versions of the tools, see the Xilinx
Design Tools: Release Notes Guide.
7. Supports only 7 series devices.
© Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. AMBA is a trademark of ARM in the EU and other countries. All other trademarks are the property of
their respective owners.
DS711 July 25, 2012
www.xilinx.com
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Product Specification