DS711 Datasheet, PDF (15/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 3: Parameter-I/O Signal Dependencies (Cont’d)
Generic
or Port
Name
Affects Depends Relationship Description
G8
C_SPLB_SUPPORT_BURSTS
P44,
P46 to
P49,
P58,
P62,
P64 to
P67,
P71,
P77,
P78
When burst support is disabled, the
AXI4-Lite interface is used and
signals that are used for AXI4
interface are not used.
G9
C_SPLB_SUPPORT_CACHELINE
C_SPLB_SUPPORT_CACHELINE
G8
is valid only when
C_SPLB_SUPPORT_BURSTS = 1.
G28
C_SPLB_BRIDGE_BASEADDR
G8, G34
C_SPLB_BRIDGE_BASEADDR is
valid only when C_EN_ERR_REGS
= 1 and
C_SPLB_SUPPORT_BURSTS = 1.
G29
C_SPLB_BRIDGE_HIGHADDR
G8, G34
C_SPLB_BRIDGE_HIGHADDR is
valid only when C_EN_ERR_REGS
= 1 and
C_SPLB_SUPPORT_BURSTS = 1.
G30
C_M_AXI_THREAD_ID_WIDTH
C_M_AXI_THREAD_ID_WIDTH is
G8
valid only when
C_SPLB_SUPPORT_BURSTS = 1.
G31
C_M_AXI_SUPPORTS_THREADS
C_M_AXI_SUPPORTS_THREADS
G8
is valid only when
C_SPLB_SUPPORT_BURSTS = 1.
G33
C_M_AXI_DATA_WIDTH
G4, G8
C_M_AXI_DATA_WIDTH is the
same as
C_SPLB_NATIVE_DWIDTH when
C_SPLB_SUPPORT_BURSTS = 1.
It is fixed at 32 when
C_SPLB_SUPPORT_BURSTS = 0.
G33
C_M_AXI_DATA_WIDTH
P53, P54, Affects the number of bits of read
P72
and write data bus and byte enables
G34
C_EN_ERR_REGS
C_M_AXI_SUPPORTS_
G8
THREADS is valid only when
C_SPLB_SUPPORT_BURSTS = 1.
I/O Signals
P3
Interrupt
Interrupt signal is available only
-
G8, G34 when C_EN_ERR_REG = 1 and
C_SPLB_SUPPORT_BURSTS = 1.
P6
SPLB_masterID[0:C_SPLB_MID_WIDTH - 1]
-
G6
Width of the SPLB_mastedID varies
according to
C_SPLB_MID_WIDTH.
P8
SPLB_BE[0 : (C_SPLB_DWIDTH/8) -1]
-
G3
Width of the SPLB_BE varies
according to C_SPLB_DWIDTH
P11
SPLB_wrDBus[0 : C_SPLB_DWIDTH - 1]
-
G3
Width of the SPLB_wrDBus varies
according to C_SPLB_DWIDTH.
DS711 July 25, 2012
www.xilinx.com
15
Product Specification