DS711 Datasheet, PDF (11/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 2: Design Parameters (Cont’d)
Generic Feature/Description
Range1 non-secure or secure
access
G14
0 = Secure normal data access
1 = Non-secure normal data
access
G15
Range1 cache encoding
See Cache Support for details.
G16
PLB base address for address
range 2
G17
PLB high address for address
range 2
Range 2 non-secure or secure
access
G18
0 = Secure normal data access
1 = Non-secure normal data
access
G19
Range2 cache encoding
See Cache Support for details.
G20
PLB base address for address
range 3
G21
PLB high address for address
range 3
Range 3 non-secure or secure
access
G22
0 = Secure normal data access
1 = Non-secure normal data
access
G23
Range3 cache encoding
See Cache Support for details.
G24
PLB base address for address
range 4
G25
PLB high address for address
range 4
Range 4 non-secure or secure
access
G26
0 = Secure normal data access
1 = Non-secure normal data
access
G27
Range4 cache encoding
See Cache Support for details.
Bridge Base Address when
G28
internal debug registers are
enabled
Bridge High Address when
G29
internal debug registers are
enabled
Parameter Name
Allowable
Values
C_SPLB_RNG1_
NONSEC_SEC⁽⁷⁾
0-1
C_SPLB_RNG1_
CACHEABLE_BUFFERABLE⁽⁸⁾
0-3
C_SPLB_RNG2_BASEADDR Valid address⁽⁵⁾
C_SPLB_RNG2_HIGHADDR Valid address⁽⁶⁾
C_SPLB_RNG2_
NONSEC_SEC⁽⁷⁾
0-1
C_SPLB_RNG2_CACHEABLE
_BUFFERABLE⁽⁸⁾
0-3
C_SPLB_RNG3_BASEADDR Valid address⁽⁶⁾
C_SPLB_RNG3_HIGHADDR Valid address⁽⁶⁾
C_SPLB_RNG3_
NONSEC_SEC⁽⁷⁾
0-1
C_SPLB_RNG3_CACHEABLE
_BUFFERABLE⁽⁸⁾
0-3
C_SPLB_RNG4_BASEADDR Valid address⁽⁵⁾
C_SPLB_RNG4_HIGHADDR Valid address⁽⁶⁾
C_SPLB_RNG4_
NONSEC_SEC⁽⁷⁾
0-1
C_SPLB_RNG4_CACHEABLE
_BUFFERABLE⁽⁸⁾
0-3
C_SPLB_BRIDGE_
BASEADDR
Valid address⁽⁹⁾
C_SPLB_BRIDGE_
HIGHADDR
Valid address⁽⁹⁾
Default VHDL
Values Type
1
integer
0
None⁽⁴⁾
None⁽⁴⁾
integer
std_logic
_vector
std_logic
_vector
1
integer
0
None⁽⁴⁾
None⁽⁴⁾
integer
std_logic
_vector
std_logic
_vector
1
integer
0
None⁽⁴⁾
None⁽⁴⁾
integer
std_logic
_vector
std_logic
_vector
1
integer
0
integer
None⁽⁴⁾
std_logic
_vector
None⁽⁴⁾
std_logic
_vector
DS711 July 25, 2012
www.xilinx.com
11
Product Specification