DS711 Datasheet, PDF (24/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Table 12: Device Interrupt Enable Register (DIER) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 to 30
Unused
N/A
0
Unused
BAR Interrupt Enable:
Interrupt Enable bit for routing BAR error to the System Interrupt
29
BIE ⁽¹⁾
Read/Write ’0’
Controller.
’1’ = Interrupt asserts in response to BAR Error
’0’ = Interrupt does not assert in response to BAR Error
30
DIE
Read/Write ’0’
DECERR Interrupt Enable:
Interrupt Enable bit for routing Decode error to the System Interrupt
Controller.
’1’ = Interrupt asserts in response to DECERR
’0’ = Interrupt does not assert in response to DECERR
31
SIE
Read/Write ’0’
SLVERR Interrupt Enable:
Interrupt Enable bit for routing Slave error to the System Interrupt
Controller.
’1’ = Interrupt asserts in response to SLVERR
’0’ = Interrupt does not assert in response to SLVERR
Notes:
1. BAR error is applicable for only burst transfers. This bit is not used when C_SPLB_SUPPORT_BURSTS = 0.
Bridge Transaction Translation
Table 13 shows translation of PLBV46 transaction to AXI transactions. For one PLB transaction, two AXI
transactions must be requested when a 4 KB cross is detected in a PLB transfer. AXI allows WRAP type burst
transactions of 2, 4, 8, and 16 words; however, PLB only supports 4, 8 word line transactions.
When C_SPLB_NATIVE_DWIDTH = 64, the M_AXI_DATA_WIDTH is set to 64, and a 32-bit PLB master request of
a word burst of length 16 is sent on AXI as a INCR burst transfer of length 16 with a burst size 4 bytes in transfer (as
a narrow transfer).
When C_SPLB_NATIVE_DWIDTH = 32, the M_AXI_DATA_WIDTH is set to 32 and a 64-bit PLB master request of
a double word burst of length 16 is sent on AXI as a INCR burst transfer of burst length 32 with a burst size 4 bytes
as the maximum burst length supported on AXI4 is 256.
Table 13: PLB Transaction to AXI Transaction
PLB Transaction
AXI Transaction
Single read or write of 1 to Burst read or write of INCR type with burst length
4 bytes on a 32-bit PLB as 1.
Single read or write of 1 to Burst read or write of INCR type with burst length
8 bytes on a 64-bit PLB as 1.
Description
When PLB issues a single read with 1/2/3
bytes enabled, AXI issues it as INCR burst
with burst length 1 and burst size 2 (number
of bytes as 4) and controls strobes during
writes and discards the unused bytes during
read.
When PLB issues a single read with 1 to 7
bytes enabled, AXI issues it as INCR burst
with burst length 1 and burst size 3(number
of bytes as 8) and controls strobes during
writes and discards the unused bytes during
read
DS711 July 25, 2012
www.xilinx.com
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Product Specification