DS711 Datasheet, PDF (2/42 Pages) Xilinx, Inc – LogiCORE IP PLBV46 to AXI

LogiCORE IP PLBV46 to AXI Bridge (v2.01.a)
Not Supported Features and Limitations
PLBV46 Slave Interface
• PLB master size greater than 64 bits
The following PLB features and behaviors are not supported because the Xilinx simplification of the PLBV46 does
not support them:
• Aborts
• Non-Memory transfer types (DMA Flyby, Buffered, peripheral to memory, memory to peripheral and DMA
memory to memory are ignored)
• Fixed length burst transfer requests of 17 to 256 data beats
• Fixed length bursts of size byte and half word
• Premature fixed length burst terminations
• Indeterminate burst transfers
• Cache line transfers of 16 words
• Parity
• Transfer attributes
• PLB bus locked transfers
• Pending request and priority input information
• Slave to master interrupts
AXI Master Interface
• Interface initialization is not supported.
• Quality of service signalling is not supported.
The following AXI features are not supported as PLBV46 never generates them:
• FIXED Burst type is not supported.
• AXI cache support is limited.
• Bufferable and cacheable attributes can be selected during configuration.
• Read allocate and write allocate attributes are not supported.
• Protection unit support is limited.
• Privileged and instruction accesses are not supported.
• Either secure or non-secure is selected during configuration.
• Atomic exclusive transactions and lock transactions are not supported. All the AXI transactions are normal
accesses.
• Unaligned transfers are not supported.
• Barrier transfers/Debug transfers/User signals are not supported.
DS711 July 25, 2012
www.xilinx.com
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Product Specification