DS698 Datasheet, PDF (9/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
XPS InSystem Flash IP Core Register Descriptions
There are no separate registers for XPS InSystem Flash IP Core. All the XPS SPI IP Core registers are
accessed through the XPS InSystem Flash IP Core.
Table 4 gives a summary of the XPS SPI IP Core internal registers, accessed through the XPS InSystem
Flash IP Core. The transmit FIFO occupancy register and the receive FIFO occupancy register exists
only when C_FIFO_EXIST = 1.
Table 4: XPS SPI IP Core Registers
Base Address +
Offset (hex)
Register Name
Access
Type
Default
Value
(hex)
Description
SPI Core Grouping
C_BASEADDR + 40 SRR
Write
N/A
Software Reset Register
C_BASEADDR + 60 SPICR
R/W
0x180 SPI Control Register
C_BASEADDR + 64 SPISR
Read
0x5
SPI Status Register
C_BASEADDR + 68 SPIDTR
Write
0x0
SPI Data Transmit Register
A single register or a FIFO
C_BASEADDR + 6C SPIDRR
Read
0x0
SPI Data Receive Register
A single register or a FIFO
C_BASEADDR + 70 SPISSR
R/W
No slave is
selected
SPI Slave Select Register
C_BASEADDR + 74
SPI Transmit FIFO
Occupancy Register⁽¹⁾
Read
0x0
Transmit FIFO Occupancy
Register
C_BASEADDR + 78
SPI Receive FIFO
Occupancy Register⁽¹⁾
Read
0x0
Receive FIFO Occupancy
Register
Interrupt Controller Grouping
C_BASEADDR + 1C DGIER
C_BASEADDR + 20 IPISR
R/W
R/TOW⁽²⁾
0x0
Device Global Interrupt
Enable Register
0x0
IP Interrupt Status Register
C_BASEADDR + 28 IPIER
R/W
0x0
IP Interrupt Enable Register
Notes:
1. This register does not exist if C_FIFO_EXIST = 0.
2. TOW = Toggle On Write. Writing a 1 to a bit position within the register causes the corresponding bit position
in the register to toggle.
DS698 September 16, 2009
www.xilinx.com
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Product Specification