DS698 Datasheet, PDF (17/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Table 12: SPI Receive FIFO Occupancy Register Description (C_BASEADDR + 0x78)
Bit(s)
Name
Core Reset Value
Access
(hex)
Description
0 - 27 Reserved
N/A
N/A
Reserved
28 - 31 Occupancy Value
Read
0
Bit 28 is the MSB. The binary value plus 1 yields
the occupancy.
XPS InSystem Flash IP Core Interrupt Descriptions
The XPS InSystem Flash IP Core has instantiated XPS SPI IP Core which supports number of distinct
interrupts that are sent to the interrupt controller module which is one of the sub-modules of XPS SPI
IP Core. The Interrupt controller module allows each interrupt to be enabled independently (via the IP
interrupt enable register (IPIER)).
The interrupt registers are in the interrupt module. The XPS InSystem Flash IP Core permits multiple
conditions for an interrupt, or an interrupt strobe which occurs only after the completion of a transfer.
Setting the parameter C_FIFO_EXIST = 1 makes available all the interrupts shown in Table 14.
Setting the parameter C_FIFO_EXIST = 0 makes available all the interrupts except bit(25), i.e. Tx FIFO
Half Empty, which is not present in this case.
Device Global Interrupt Enable Register (DGIER)
The Device Global Interrupt Enable Register is used to globally enable the final interrupt output from
the Interrupt controller as shown in Figure 10 and described in Table 13. This bit is a read/write bit and
is cleared upon reset.
Figure Top x-ref 10
GIE
Reserved
01
31
DS698_10_072709
Figure 10: Device Global Interrupt Enable Register (C_BASEADDR + 0x1C)
Table 13: Device Global Interrupt Enable Register (DGIER) Description(C_BASEADDR + 0x1C)
Bit(s)
0
1 - 31
Name Access
GIE
R/W
Reserved
N/A
Reset
Value
’0’
N/A
Description
Global Interrupt Enable. It enables all individually enabled
interrupts to be passed to the interrupt controller.
’0’ = Disabled
’1’ = Enabled
Reserved
IP Interrupt Status Register (IPISR)
Up to seven unique interrupt conditions are possible depending upon whether the system is
configured with FIFOs or not. A system without FIFOs has six interrupts.
Please note that these are total number of interrupts XPS SPI IP Core supports internally. As for XPS
InSystem Flash core XPS SPI IP Core is configured only in master SPI mode, some of the slave operation
related interrupt signals may not be useful at all.
DS698 September 16, 2009
www.xilinx.com
17
Product Specification