DS698 Datasheet, PDF (8/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
XPS InSystem Flash IP Core Parameter - Port Dependencies
The dependencies between the XPS InSystem Flash IP Core design parameters and I/O signals are
described in Table 3.
Table 3: XPS InSystem Flash IP Core Parameter-Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G5
C_SPLB_DWIDTH
P8, P11,
P34
-
Affects the number of bits in data bus
G7
C_SPLB_MID_WIDTH
This value is calculated as:
P6
G8
log₂(C_SPLB_NUM_MASTERS) with a
minimum value of 1
G8
C_SPLB_NUM_MASTERS
P37, P38,
P39, P43
-
Affects the number of PLB masters
I/O Signals
P6
PLB_masterID[0 :
C_SPLB_MID_WIDTH - 1]
-
G7
Width of the PLB_mastedID varies
according to C_SPLB_MID_WIDTH
P8
PLB_BE[0 :
(C_SPLB_DWIDTH/8) -1]
-
G5
Width of the PLB_BE varies according to
C_SPLB_DWIDTH
P11
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
-
G5
Width of the PLB_wrDBus varies
according to C_SPLB_DWIDTH
P34
Sl_rdDBus[0 :
C_SPLB_DWIDTH - 1]
-
G5
Width of the Sl_rdDBus varies according
to C_SPLB_DWIDTH
Sl_MBusy[0 :
P37 C_SPLB_NUM_MASTERS
-
- 1]
G8
Width of the Sl_MBusy varies according to
C_SPLB_NUM_MASTERS
Sl_MWrErr[0 :
P38 C_SPLB_NUM_MASTERS
-
- 1]
G8
Width of the Sl_MWrErr varies according
to C_SPLB_NUM_MASTERS
Sl_MRdErr[0 :
P39 C_SPLB_NUM_MASTERS
-
- 1]
G8
Width of the Sl_MRdErr varies according
to C_SPLB_NUM_MASTERS
Sl_MIRQ[0 :
P43 C_SPLB_NUM_MASTERS
-
- 1]
G8
Width of the Sl_MIRQ varies according to
C_SPLB_NUM_MASTERS
8
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DS698 September 16, 2009
Product Specification