DS698 Datasheet, PDF (21/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Table 15: IP Interrupt Enable Register (IPIER) Description (C_BASEADDR + 0x28) (Contd)
Bit(s)
Name
31 MODF
Access
R/W
Reset
Value
’0’
Description
Mode-Fault Error Flag.
’0’ = Disabled
’1’ = Enabled
Note: As XPS InSystem Flash IP Core operates in
the master SPI mode only, this bit must be always set
to ’0’.
XPS InSystem Flash IP Core Design Description
SPI Device Features
In addition to the features listed in the Features section, the SPI device also includes the following
standard features:
• Single-master environment supported
• Single-slave environment supported. Only one ISF SPI slave device is supported.
• Supports maximum SPI clock rates up to one-half of the PLB clock rate. (Please check the ISF timing
requirements from Spartan-3AN FPGA In System Flash User Guide, UG333).
• Parameterizable baud rate generator.
• Back to Back transactions are supported, which means there can be multiple byte transfers taking
place without interruption provided the transmit FIFO never gets empty and receive FIFO never
gets full.
• All SPI transfers are full-duplex where an 8-bit data character is transferred from the master to the
slave and an independent 8-bit data character is transferred from the slave to the master. This can
be viewed as a circular 16-bit shift register; an 8-bit shift register in the SPI master device and
another 8-bit shift register in a SPI slave device that are connected.
Optional FIFOs
Please note that the implementation of FIFO is a part of XPS SPI IP Core. So following explaination
holds true for XPS InSystem Flash IP Core.
The user has the option to include FIFOs in the XPS InSystem Flash IP Core as shown in Figure 1. These
FIFO’s are internally configured from XPS SPI IP Core. Since SPI is full-duplex, both transmit and re-
ceive FIFOs are instantiated as a pair.
When FIFOs are implemented, the slave select address is required to be the same for all data buffered
in the FIFOs. This is required because a FIFO for the slave select address is not implemented. Both
transmit and receive FIFOs are 16 elements deep and are accessed via single PLB transactions since
burst mode is not supported.
The transmit FIFO is write-only. When data is written in the FIFO, the occupancy number is
incremented and when an SPI transfer is completed, the number is decremented. As a consequence of
this operation, aborted SPI transfers still has the data available for the transmission retry. The transfers
can only be aborted in the master mode by setting Master Transaction Inhibit bit, bit(23) of SPICR to ’1’
during a transfer. Setting this bit in the slave mode has no affect on the operation of the slave. These
aborted transfers are on the SPI interface. The occupancy number is a read-only register.
DS698 September 16, 2009
www.xilinx.com
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Product Specification