DS698 Datasheet, PDF (27/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
8. An option is implemented in this FPGA design to implement FIFOs on both transmit and receive
(Full Duplex only) mode.
9. M68HC11 implementation supports only byte transfer.
10. The baud rate generator is specified by Motorola to be programmable via bits in the control
register; however, in this FPGA design the baud rate generator is programmable via parameters in
the VHDL implementation. Thus, in this implementation run time configuration of baud rate is not
possible. Furthermore, in addition to the ratios of 2, 4, 16 and 32, all integer multiples of 16 up to
2048 are allowed.
Reference Documents
The following documents contain reference information important to understanding the XPS InSystem
Flash IP Core design:
1. DS561 PLBV46_Slave_Single
2. DS570 XPS SPI
3. UG331 Spartan-3A Generation FPGA User Guide
4. UG333 Spartan-3AN FPGA In-System Flash User Guide
5. Motorola M68HC11-Rev. 4.0 Reference Manual
6. Motorola MPC8260 PowerQUICC II™ Users Manual 4/1999 Rev. 0
7. IBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification (v4.6).
Revision History
Date
05/22/08
01/05/09
05/16/09
9/16/09
Version
1.0
1.1
1.2
1.3
Revision
Initial version
Updated version
Updated minor version as its base core xps_spi goes through minor version update
Updated to v1.01b for EDK_L 11.3 release; updated legal matter and images; added
legal disclaimer;
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DS698 September 16, 2009
www.xilinx.com
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Product Specification