DS698 Datasheet, PDF (24/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
11. Write all ones to SPISSR or exit manual slave select assert mode to deassert SS vector while SCK
and MOSI are in the idle state.
12. Disable XPS InSystem Flash IP Core as desired.
XPS InSystem Flash IP Core in SPI master mode without FIFOs and ISF as slave device performing
single command (example: ISF status read command, which is of 4 bytes) transfer.
Follow these steps to successfully complete an SPI transaction:
1. Configure master DGIER and IPIER. Also configure slave DGIER and IPIER registers as desired.
2. Write configuration data to master SPI device SPICR as required. Do not enable the core at this
moment. This can be done by setting the Master Transaction Inhibit bit to 1.
3. Write data to SPIDTR register.
4. Write into the SPICR to set the SPE bit to ’1’ to start the transmission.
5. Write the active-low, one-hot encoded ISF slave select address to the master SPISSR.
6. Write the SPICR (disable the Master Transaction Inhibit)to start the data transmission.
7. Update the SPIDTR with the next byte of data and Read the SPIDRR.
8. Wait for interrupt (typically IPISR bit(30)) or poll status for completion.
9. Read IPISR of the core.
10. Perform interrupt request service routine as required.
11. Repeat the step from 4 till the complete 4 bytes are transferred.
12. Perform actions as required or dictated by SPISR data, which also includes reading the data from
SPIDRR register.
Design Constraints
Note: An example UCF for this core is available and must be modified for use in the system. Please
refer to the EDK Getting Started Guide for the location of this file.
Timing Constraints
For complete timing coverage, it is recommended that Flip-Flop edge to edge constraint is specified
along with SPLB_Clk input constraint. An example is shown in Figure 13.
Figure Top x-ref 13
NET "SPLB_CLK" TNM_NET = "splb_clk";
TIMESPEC "TS_splb_clk" = PERIOD "splb_clk" 10 ns HIGH 50%;
NET "*XPS_InSystem_FLASH_I/XPS_SPI_MODULE_I/I_SPI_MODULE/Serial_Dout" TIG;
NET "*XPS_InSystem_FLASH_I/XPS_SPI_MODULE_I/I_SPI_MODULE/SS_O<0>" TIG;
NET "XPS_InSystem_FLASH_I/miso_from_isf" TIG;
DS698_13_072709
Figure 13: Timing Constraints
Design Implementation
Target Technology
The intended target technology is the Spartan-3an FPGA family.
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DS698 September 16, 2009
Product Specification