DS698 Datasheet, PDF (22/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
If a write is attempted when the FIFO is full, then acknowledgement is given along with an error signal
generation. Interrupts associated with the transmit FIFO include data transmit FIFO empty, transmit
FIFO half empty and transmit FIFO under-run. See the section on XPS InSystem Flash IP Core Interrupt
Descriptions for details.
The receive FIFO is read-only. When data is read from the FIFO, the occupancy number is decremented
and when the SPI transfer is completed, the number is incremented. If a read is attempted when the
FIFO is empty, then acknowledgement is given along with an error signal generation. When the receive
FIFO becomes full, the receive FIFO full interrupt is generated.
Data is automatically written to the FIFO from the SPI module shift register after the completion of the
SPI transfer. If the receive FIFO is full and more data is received, then a receive FIFO overflow interrupt
is issued. When this happens, all data attempted to be written to the full receive FIFO by the SPI
module is lost.
SPI transfers, when the XPS InSystem Flash IP Core is configured with FIFOs, can be started in two
different ways depending on when the enable bit in the SPICR is set. If the enable bit is set prior to the
first data being loaded in the FIFO, then the SPI transfer begins immediately after the write to the
master transmit FIFO. If the FIFO is emptied via SPI transfers before additional elements are written to
the transmit FIFO, an interrupt will be asserted. When the PLB to SPI SCK frequency ratio is sufficiently
small, this scenario is highly probable.
Alternatively, the FIFO can be loaded up to 16 elements and then the enable bit can be set which starts
the SPI transfer. In this case, an interrupt is issued after all elements are transferred. In all cases, more
data can be written to the transmit FIFOs to increase the number of elements transferred before
emptying the FIFOs.
Local Master Loopback Operation
Local master loopback operation, although not included in the M68HC11 reference manual, has been
implemented to expedite core internal testing. This operation is selected via setting the loop bit in the
SPICR, the transmitter output is internally connected to the receiver input. The receiver and transmitter
operate normally, except that received data (from remote slave) is ignored.
Hardware Error Detection
Under-run and over-run conditions error detection is provided as well. Under-run conditions can
happen only if XPS SPI IP Core is configured in slave mode operation. As for XPS InSystem Flash IP
Core, the XPS SPI IP Core is configured in master mode always, the under-run error will not occur. so
no under-run related interrupts will be generated. Over-run can happen to both master and slave
devices where a transfer occurs when the receive register or FIFO is full. During an over-run condition,
the data received in that transfer is not registered (i.e. it is lost) and the IPISR over-run interrupt bit(26)
is asserted.
Precautions to be Taken while Assigning the C_SCK_RATIO Parameter
XPS InSystem Flash IP Core is tested in hardware with the ISF (on Spartan-3AN family devices only).
Please read the data sheet of targeted Spartan-3AN FPGA family device for ISF size and other timing
related parameters. It is user’s responsibility to mention the correct values while deciding the PLB
clock and selecting the C_SCK_RATIO parameter of the core. The PLB clock and the C_SCK_RATIO
will decide the clock at SCK pin of XPS InSystem Flash IP Core.
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DS698 September 16, 2009
Product Specification