DS698 Datasheet, PDF (3/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
register. This allows transfers of an arbitrary number of elements without toggling the slave select line
between elements. However, the user must toggle the slave select line before starting a new transfer.
The XPS InSystem Flash IP Core supports continuous transfer mode, when configured as master, the
transfer continues till the data is available in transmit register/FIFO.
The XPS InSystem Flash IP Core is always configured as a SPI master and should not be configured as
slave for its proper operation. The XPS InSystem Flash IP Core is targeted to access only one In System
Flash (ISF) available on Spartan-3AN family devices.
The XPS InSystem Flash IP Core can’t communicate with off-chip SPI slave devices as the SPI interface
signals won’t come out of the core. The number of slaves is limited to 1, as this IP Core is targeted to be
used only with single ISF present on Spartan-3AN family devices.
All the other SPI and INTR registers are 32-bit wide. The XPS InSystem Flash IP Core supports only
word access to all SPI and INTR register modules.
The XPS InSystem Flash IP Core modules are described in the sections below.
XPS SPI IP Core Module:
The XPS SPI IP Core is used as base core and it is instantiated in the core. The XPS SPI IP Core contains
the following modules,-
• PLB Interface Module
The PLB Interface Module provides the interface to the PLB V4.6. The read and write transactions at the
PLB are translated into equivalent IP Interconnect (IPIC) transactions. The register interfaces of the SPI
connect to the IPIC. The PLB Interface Module also provides an address decoding service for XPS
InSystem Flash Core.
• SPI Register Module
The SPI Register Module includes all memory mapped registers (as shown in Figure 1). It interfaces to
the PLB. It consists of Status Register, Control Register, N-bit Slave Select Register (N ≤ 32) and a pair
of Transmit/Receive Registers.
• INTR Register Module
The INTR Register Module consists of interrupt related registers namely Device Global Interrupt
Enable Register (DGIER), IP Interrupt Enable Register (IPIER) and IP Interrupt Status Register (IPISR).
• SPI Module
The SPI Module consists of a shift register, a parameterized baud rate generator (BRG) and a control
unit. It provides the SPI interface, including the control logic and initialization logic. It is the heart of
XPS SPI IP Core.
• Optional FIFOs
The Tx FIFO and Rx FIFO are implemented on both transmit and receive paths when enabled by the
parameter C_FIFO_EXIST. The width of Tx FIFO and Rx FIFO depends on generic
C_NUM_TRANSFER_BITS. The depth of these FIFO’s is 16.
In System Flash Instance (Unisim Component):
The ISF (In System Flash) is a unisim library component named as SPI_ACCESS and it is instantiated in
the core. This is available only on the Spartan-3AN devices. The ISF provides the Mode-3 SPI protocol
DS698 September 16, 2009
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