DS698 Datasheet, PDF (6/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
XPS InSystem Flash IP Core I/O Signals
The XPS InSystem Flash IP Core I/O signals are listed and described in Table 2.
Table 2: XPS InSystem Flash IP Core I/O Signal Descriptions⁽¹⁾
Port
Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 SPLB_Clk
System
I
-
PLB clock
P2 SPLB_Rst
System
I
-
PLB reset, active high
P3 IP2INTC_Irpt
System
O
0
Interrupt control signal from SPI
P4 PLB_ABus[0 : 31]
P5 PLB_PAValid
P6
PLB_masterID[0 :
C_SPLB_MID_WIDTH - 1]
PLB Master Interface Signals
PLB
I
-
PLB
I
-
PLB
I
-
PLB address bus
PLB primary address valid
PLB current master identifier
P7 PLB_RNW
P8
PLB_BE[0 :
(C_SPLB_DWIDTH/8) - 1]
PLB
I
PLB
I
-
PLB read not write
-
PLB byte enables
P9 PLB_size[0 : 3]
PLB
I
-
PLB size of requested transfer
P10 PLB_type[0 : 2]
PLB
I
-
PLB transfer type
P11
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
I
-
PLB write data bus
Unused PLB Master Interface Signals
P12 PLB_UABus[0 : 31]
PLB
I
-
PLB upper address bits
P13 PLB_SAValid
P14 PLB_rdPrim
PLB
I
PLB
I
-
PLB secondary address valid
-
PLB secondary to primary read
request indicator
P15 PLB_wrPrim
P16 PLB_abort
PLB
I
PLB
I
-
PLB secondary to primary write
request indicator
-
PLB abort bus request
P17 PLB_busLock
PLB
I
-
PLB bus lock
P18 PLB_MSize[0 : 1]
PLB
I
-
PLB data bus width indicator
P19 PLB_lockErr
PLB
I
-
PLB lock error
P20 PLB_wrBurst
P21 PLB_rdBurst
P22 PLB_wrPendReq
P23 PLB_rdPendReq
P24 PLB_wrPendPri[0 : 1]
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
-
PLB burst write transfer
-
PLB burst read transfer
-
PLB pending bus write request
-
PLB pending bus read request
-
PLB pending write request priority
P25 PLB_rdPendPri[0 : 1]
PLB
I
-
PLB pending read request priority
6
www.xilinx.com
DS698 September 16, 2009
Product Specification