DS698 Datasheet, PDF (12/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Table 6: SPI Control Register (SPICR) Description (C_BASEADDR + 0x60) (Contd)
Bit(s)
Name
Core Reset
Access Value
Description
26 Tx FIFO Reset
Transmit FIFO Reset. When written to ’1’, this bit
forces a reset of the Transmit FIFO to the empty
condition. One PLB clock cycle after reset, this bit
R/W
’0’
is again set to ’0’.
This bit is unassigned when the XPS InSystem
Flash IP Core is not configured with FIFOs.
’0’ = Transmit FIFO normal operation
’1’ = Reset transmit FIFO pointer
27 CPHA
Clock Phase. Setting this bit selects one of two
fundamentally different transfer formats.
R/W
’0’ The ISF supports SPI Mode-3 protocol. To operate
the ISF properly, it is required to set this bit to ’1’
during the core configuration.
28 CPOL
Clock Polarity. Setting this bit defines clock
polarity.
’0’ = Active high clock; SCK idles low
R/W
’0’ ’1’ = Active low clock; SCK idles high
The ISF supports SPI Mode-3 protocol. To operate
the ISF properly, it is required to set this bit to ’1’
during the core configuration.
29 Master
Master. Setting this bit configures the SPI device
as a master or a slave.
’0’ = Slave configuration
R/W
’0’ ’1’ = Master configuration
To operate the core in master SPI mode, it is must
to set this bit to ’1’ during the core configuration.
No SPI slave mode is supported.
30 SPE
SPI System Enable. Setting this bit to ’1’ enables
the SPI devices as noted below.
’0’ = SPI system disabled.
’1’ = SPI system enabled. Master outputs active
(e.g. MOSI and SCK in idle state) and slave
R/W
’0’ outputs will become active if SS becomes
asserted. Master will start transfer when transmit
data is available.
To operate the ISF properly, please follow
configuration steps mentioned in SPI Registers
Flow Description.
31 LOOP
Local Loopback Mode. Enables local loopback
operation and is functional only in master mode.
’0’ = Normal operation
’1’ = Loopback mode. The transmitter output is
R/W
’0’
internally connected to the receiver input. The
receiver and transmitter operate normally, except
that received data (from remote slave) is ignored.
Please make sure that the ISF is is not selected
during the internal loop-back mode, else it will
result in error condition.
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DS698 September 16, 2009
Product Specification