DS698 Datasheet, PDF (20/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
IP Interrupt Enable Register (IPIER)
The IPIER has an enable bit for each defined bit of the IPISR as shown in Figure 12 and described in
Table 15. All bits are cleared upon reset.
Figure Top x-ref 12
Reserved
DRR
Full
Tx FIFO
DTR
Half Empty
Empty MODF
0
24 25 26 27 28 29 30 31
DRR
Slave
Over-run
MODF
DTR
Under-run
DS698_12_072709
Figure 12: IP Interrupt Enable Register (IPIER) (C_BASEADDR + 0x28)
Table 15: IP Interrupt Enable Register (IPIER) Description (C_BASEADDR + 0x28)
Bit(s)
Name
0 - 24 Reserved
Access
N/A
25 Tx FIFO Half Empty R/W
26 DRR Over-run
R/W
27 DRR Full
R/W
28 DTR Under-run
R/W
29 DTR Empty
R/W
30 Slave MODF
R/W
Reset
Value
N/A
’0’
’0’
’0’
’0’
’0’
’0’
Description
Reserved
Transmit FIFO Half Empty.
’0’ = Disabled
’1’ = Enabled
Receive FIFO Over-run.
’0’ = Disabled
’1’ = Enabled
Note: Please make sure that the XPS InSystem
Flash IP Core is configured only in the master SPI
mode.
Data Receive Register/FIFO Full.
’0’ = Disabled
’1’ = Enabled
Data Transmit FIFO Under-run.
’0’ = Disabled
’1’ = Enabled
Note: As XPS InSystem Flash IP Core operates in
the master SPI mode only, this bit must be always tied
to ’0’.
Data Transmit Register/FIFO Empty.
’0’ = Disabled
’1’ = Enabled
Slave Mode-Fault Error Flag.
’0’ = Disabled
’1’ = Enabled
Note: As XPS InSystem Flash IP Core operates in
the master SPI mode only, this bit must be always set
to ’0’.
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DS698 September 16, 2009
Product Specification