DS698 Datasheet, PDF (2/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Functional Description
The top level block diagram for the XPS InSystem Flash IP Core is shown in Figure 1.
Figure Top x-ref 1
PLB
SPI REGISTER
MODULE
Status Register
(SPISR)
SPI MODULE
BRG³
Control Register
(SPICR)
PLB
Interface
Module
Slave Select Register
(SPISSR)
Transmit Register
(SPIDTR)
Receive Register
(SPIDRR)
Tx FIFO¹
Rx FIFO¹
INTR REGISTER
MODULE
Global Interrupt Enable
Register (DGIER)
IP Interrupt Status
Register (IPISR)
IP Interrupt Enable
Register (IPIER)
Control Unit
SPI
Ports
SCK_I
SCK_O
SCK_T
MISO_I
MISO_O
MISO_T
MOSI_I
MOSI_O
MOSI_T
2
SS_O
SS_T ²
2
SS_I
SPISEL
1 = The width of Tx FIFO, Rx FIFO and *Shift Register depends on the value of generic C_NUM_TRANSFER_BITS
2 = The width of SS depends on the value of generic C_NUM_SS_BITS
3 = BRG stands for Baud Rate Generator
4= The above block diagram is same as XPS SPI core. In this core, apart from SPI ports, only SS_O, MOSI_O, MISO_I,
and SCK_O signals are useful. All remaming signals are connected with the default values,
DS698_01_072709
Figure 1: XPS InSystem Flash IP Core Top-Level Block Diagram
The XPS InSystem Flash IP Core uses XPS SPI IP Core as base core. The ISF primitive is instantiated in
the core along with the XPS SPI IP Core instantiation.
The XPS InSystem Flash IP Core provides a full-duplex synchronous channel that supports four-wire
interface (receive, transmit, clock and slave-select) between PLBv46 master and ISF.
The XPS InSystem Flash IP Core supports Manual Slave Select Mode as the Default Mode of operation.
This mode allows the user to manually control the slave select line by the data written to the slave select
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DS698 September 16, 2009
Product Specification