DS698 Datasheet, PDF (14/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Table 7: SPI Status Register (SPISR) Description (C_BASEADDR + 0x64) (Contd)
Bit(s)
Name
31 Rx_Empty
Core
Access
Read
Reset
Value
’1’
Description
Receive Empty. When a receive FIFO exists, this bit will be
set high when the receive FIFO is empty. The occupancy of
the FIFO is decremented with each FIFO read operation.
When FIFOs don’t exist, this bit is set high when the receive
register has been read. This bit is cleared at the end of a
successful SPI transfer.
SPI Data Transmit Register (SPIDTR)
This register is written with a data to be transmitted on the SPI bus. Once the SPE bit is set to ’1’ in
master mode the data is transferred from the SPIDTR to the shift register.
The SPIDTR is shown in Figure 5, while Table 8 shows specifics of the data format.
When a transmit FIFO exists, data is written directly in the FIFO and the first location in the FIFO is
treated as the SPIDTR. The pointer is decremented after completion of each SPI transfer.
This register should not be read and used only for writing when it is known that space for the data is
available. If an attempt to write is made on a full register or FIFO, then the PLB write transaction
completes with an error condition. Reading to the SPIDTR is not allowed and the read transaction will
result in undefined data.
Figure Top x-ref 5
Reserved
Tx Data (D0 - DN-1)
0
31-N 31-N+1
31
DS698_05_072709
Figure 5: SPI Data Transmit Register (C_BASEADDR + 0x68)
Table 8: SPI Data Transmit Register (SPIDTR) Description (C_BASEADDR + 0x68)
Bit(s)
Name
Core Reset
Access Value
Description
0 - [31-N]
Reserved
N/A
N/A Reserved
N-bit SPI transmit data. N is only 8. The bit postion
[31-N+1] - 31 Tx Data⁽¹⁾ (D₀ - D_N-1)
Write
only
0
31 represents N-1 data bit. The ISF supports 8-bit
transfer mode only.
N = 8 as C_NUM_TRANSFER_BITS = 8
Notes:
1. The D_N-1 bit will always represent the MSB bit irrespective of "LSB first" or "MSB first" transfer selection.
SPI Data Receive Register (SPIDRR)
This register is used to read data that is received from the SPI bus. This is a double buffered register. The
received data is placed in this register after each complete transfer. The SPI architecture does not
provide any means for a slave to throttle traffic on the bus; consequently, the SPIDRR is updated
following each completed transaction only if the SPIDRR was read prior to the last SPI transfer. If the
SPIDRR was not read (i.e. is full), then the most recently transferred data will be lost and a receive
over-run interrupt will occur. The same condition can occur with a master SPI device as well.
14
www.xilinx.com
DS698 September 16, 2009
Product Specification