DS698 Datasheet, PDF (5/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Table 1: XPS InSystem Flash IP Core Design Parameters (Contd)
Generic Feature/Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
G15
Select the subfamily of
Spartan-3AN devices
C_DEVICE ⁽¹⁾⁽⁷⁾
"3S50AN",
"3S200AN",
"3S400AN",
"3S700AN",
"3S1400AN"
"3S700AN" string
G16
HEX file containing the
memory initialization
contents
C_SIM_MEM_FILE⁽¹⁾ Any file and directory
(8)
name
"NONE"
string
G17 64-byte value
G18 64-byte value
G19
Choice of simulation
delays for ISF
C_SIM_FACTORY_
ID⁽¹⁾⁽⁹⁾
C_SIM_USER_ID⁽¹⁾⁽¹
0)
Any 64-byte value
Any 64-byte value
C_SIM_DELAY_TYP "SCALED"⁽¹¹⁾,
E
"ACCURATE"
all ’0’
all ’1’
"SCALED"
bit_
vector
bit_
vector
string
Notes:
1. The in system flash (ISF) is present only on "spartan3an" FPGA family devices, which is considered to be the
part of "spartan3a" FPGA family. So when "spartan3an" family is targeted, the user must use C_FAMILY =
"spartan3a". Please refer the Spartan-3AN FPGA In System Flash User Guide, UG333(v2.0) for more
reference of ISF.
2. The range C_BASEADDR to C_HIGHADDR is the address range for the XPS InSystem Flash IP Core. This
range is subject to restrictions to accommodate the simple address decoding scheme that is employed: The
size, C_HIGHADDR - C_BASEADDR + 1, must be a power of two and must be at least 0x80 to accommodate
all XPS InSystem Flash IP Core registers. However, a larger power of two may be chosen to reduce decoding
logic. C_BASEADDR must be aligned to a multiple of the range size.
3. No default value will be specified to insure that an actual value appropriate to the system is set.
4. Point to point bus topology is not allowed.
5. Burst is not supported.
6. This parameter remains constant and user can’t modify it. This parameter is added to support the XPS SPI IP
Core parameter requirements.
7. The C_DEVICE parameter should be used along with C_FAMILY = "spartan3a". It will be auto picked up by the
EDK tool while integrating the XPS InSystem Flash IP Core in EDK system. The value for the parameter should
be one of the sub-family member of Spartan-3AN.
8. The C_SIM_MEM_FILE is an optional generic. It represents the hex file containing the memory contents for
ISF memory. Please refer the Spartan-3AN FPGA In System Flash User Guide, UG333 for more reference.
9. The C_SIM_FACTORY_ID is an optional generic. The C_SIM_FACTORY_ID is a 64-byte factory-programmed
unique indentifier number to be specified in device Security Register. Please refer the Spartan-3AN FPGA In
System Flash User Guide, UG333 for more reference.
10. The C_SIM_USER_ID is an optional generic. This a 64-byte factory-programmed unique indentifier number to
be specified in device Security Register. Please refer the Spartan-3AN FPGA In System Flash User Guide,
UG333 for more reference.
11. The C_SIM_DELAY_TYPE is an simulation-only optional generic. It is recommended that user should leave it
to the default value of "SCALED".
DS698 September 16, 2009
www.xilinx.com
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Product Specification