DS698 Datasheet, PDF (11/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Figure Top x-ref 3
0
Master
TransactionRx ^FIFO
Master
Inhibit ^{Reset CPHA}
LOOP
22 23 24 25 26 27 28 29 30 31
Reserved
LSB First
Tx FIFO
SPE
Reset
Manual Slave ^CPOL
Select Assertion
Enable
DS698_03_072709
Figure 3: SPI Control Register (C_BASEADDR + 0x60)
Table 6: SPI Control Register (SPICR) Description (C_BASEADDR + 0x60)
Bit(s)
Name
Core Reset
Access Value
Description
0 - 21 Reserved
N/A
N/A Reserved
22 LSB First
LSB First. This bit selects LSB first data transfer
format.
The default transfer format is MSB first.
R/W
’0’ ’0’ = MSB first transfer format
’1’ = LSB first transfer format
The ISF supports only MSB-to-LSB bit format. So
this bit should always be set to default ’0’.
Master Transaction Inhibit. This bit inhibits
master transactions.
23
Master Transaction
Inhibit
R/W
’1’ This bit has no effect on slave operation.
’0’ = Master transactions enabled
’1’ = Master transactions disabled
24
Manual Slave Select
Assertion Enable
R/W
Manual Slave Select Assertion Enable. This bit
forces the data in the slave select register to be
asserted on the slave select output anytime the
device is configured as a master and the device is
enabled (SPE asserted).
’1’ This bit has no effect on slave operation.
’1’ = Slave select output follows data in slave select
register
Please note that Automatic Slave Select Mode is
not supported due to In system Flash specific
requirements.
25 Rx FIFO Reset
Receive FIFO Reset. When written to ’1’, this bit
forces a reset of the Receive FIFO to the empty
condition. One PLB clock cycle after reset, this bit
R/W
’0’
is again set to ’0’.
This bit is unassigned when the XPS InSystem
Flash IP Core is not configured with FIFOs.
’0’ = Receive FIFO normal operation
’1’ = Reset receive FIFO pointer
DS698 September 16, 2009
www.xilinx.com
11
Product Specification