DS698 Datasheet, PDF (23/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
SPI Protocol Slave Select Assertion Modes
The SPI protocol is designed to have manual slave select assertion which is described in the following
sections. In XPS InSystem Flash IP Core only the manual slave mode is allowed.
SPI Protocol with Manual Slave Select Assertion
This section briefly describes the SPI protocol where slave select (SS) is manually asserted by the user
(i.e. SPICR bit(24) = 1).
This is the configuration mode provided to permit transfers of an arbitrary number of elements without
toggling slave select until all the elements are transferred. In this mode, the data in the SPISSR register
appears directly on the SS output.
As described earlier, SCK must be stable before the assertion of slave select. Therefore, when manual
slave select mode is utilized, the SPI master must be enabled first (SPICR bit(24) = 1) to assert SCK to
the idle state prior to asserting slave select.
Note that the master transfer inhibit (SPICR bit(23)) can be utilized to inhibit master transactions until
the slave select is asserted manually and all data registers of FIFOs are initialized as desired. This can be
utilized before the first transaction and after any transaction that is allowed to complete.
SPI Registers Flow Description
This section provides information on setting the SPI registers to initiate and complete bus transactions.
XPS InSystem Flash IP Core in SPI master mode with FIFOs where the ISF is selected as slave using
Slave Select Register and enabled via SPICR bit(24) assertion
This flow permits the transfer of N number of bytes by toggling of the slave select line just once. This is
the default mode of operation. Please note that only Manual Slave Select mode must be configured for
the proper operation of the core. Follow these steps to successfully complete an SPI transaction:
1. Configure DGIER and IPIER registers as desired.
2. Insure SPISSR register has all ones.
3. Write configuration data to core’s SPICR as desired including setting bit(24) for manual asserting of
SS and setting both enable bit and master transfer inhibit bit to logic ’1’. This initializes SCK and
MOSI but inhibits transfer. Make sure that the bit-27 (CPHA) and bit-28 (CPOL) of the SPICR
register are set to ’1’, this will make XPS SPI IP Core to operate in SPI Mode-3 protocol.
4. Write initial data to core’s FIFO at SPIDTR register address. At this moment it is assumed that the
SPI master is disabled.
5. Write to SPISSR to manually assert SS (Slave Select active low).
6. Write the above configuration data to master SPI device SPICR, but clear Master Inhibit Bit which
starts transfer.
7. Wait for interrupt (typically IPISR bit(30)) or poll status for completion. Wait time depends on SPI
clock ratio.
8. Set Master Transaction Inhibit bit in SPICR so that the core can service interrupt request.
9. Write new data to FIFO at SPIDTR address and then clear master transaction inhibit bit in SPICR to
continue N 8-bit element transfer. Note that an overrun of the SPIDRR FIFO can occur if the SPIDRR
FIFO is not read properly. Also note that SCK will have "stretched" idle levels between element
transfers (or groups of element transfers if utilizing FIFOs) and that MOSI can transition at end of a
element transfer (or group of transfers) but will be stable at least one-half SCK period prior to
sampling edge of SCK.
10. Repeat above steps until all data is transferred.
DS698 September 16, 2009
www.xilinx.com
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Product Specification