DS698 Datasheet, PDF (15/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
For the XPS SPI IP Core with a receive FIFO, the incoming data is buffered in the FIFO. The receive
FIFO is a read only buffer. If an attempt to read an empty receive register or FIFO is made, then the PLB
read transaction completes with an error condition. The effect is undefined if an attempt is made to
write the SPIDRR. The SPIDRR is shown in Figure 6, while the specifics of the data format is described
in Table 9.
Figure Top x-ref 6
Reserved
Rx Data (D0 - DN-1)
0
31-N 31-N+1
31
DS698_06_072709
Figure 6: SPI Data Receive Register (C_BASEADDR + 0x6C)
Table 9: SPI Data Receive Register (SPIDRR) Description (C_BASEADDR + 0x6C)
Bit(s)
Name
Core Reset
Access Value
Description
0 - [31-N]
Reserved
N/A
N/A Reserved
N-bit SPI receive data. N is only 8. The bit postion
[31-N+1] - 31 Rx Data⁽¹⁾ (D₀ - D_N-1)
Read
only
0
31 represents N-1 data bit. The ISF supports
8-bit transfer mode only.
N = 8 as C_NUM_TRANSFER_BITS = 8
Notes:
1. The D_N-1 bit will always represent the MSB bit irrespective of "LSB first" or "MSB first" transfer selection.
SPI Slave Select Register (SPISSR)
This register contains an active-low, one-hot encoded Slave Select vector SS of length N, where N is the
number of ISF slaves. In the XPS InSystem Flash IP Core the ISF is the only slave. So this register will
always be of 1-bit length. The default value is tied to ’1’. The bits of SS occupy the right-most bits of the
register.
The bit assignment in the SPISSR is shown in Figure 7 and described in Table 10.
Figure Top x-ref 7
Reserved
Selected ISF Slave
0
30 31
DS698_07_072709
Figure 7: SPI Slave Select Register (C_BASEADDR + 0x70)
Table 10: SPI Slave Select Register (SPISSR) Description (C_BASEADDR + 0x70)
Bit(s)
0 - 30
31
Name
Reserved
Selected
Slave
Core
Access
N/A
R/W
Reset
Value
N/A
1
Description
Reserved
Active-low. In order to select the ISF as slave, this bit should
be programmed to ’0’.
SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY)
The SPI Transmit FIFO Occupancy Register is present if and only if XPS InSystem Flash IP Core is
configured with FIFOs (C_FIFO_EXIST = 1). If it is present and if the Transmit FIFO is not empty, the
DS698 September 16, 2009
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Product Specification