DS698 Datasheet, PDF (7/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Table 2: XPS InSystem Flash IP Core I/O Signal Descriptions⁽¹⁾
Port
Signal Name
Interface I/O
Initial
State
Description
P26 PLB_reqPri[0 : 1]
PLB
I
-
PLB current request priority
P27 PLB_TAttribute[0 : 15]
PLB
I
-
PLB transfer attribute
PLB Slave Interface Signals
P28 Sl_addrAck
PLB
O
0
Slave address acknowledge
P29 Sl_SSize[0 : 1]
PLB
O
0
Slave data bus size
P30 Sl_wait
PLB
O
0
Slave wait
P31 Sl_rearbitrate
PLB
O
0
Slave bus rearbitrate
P32 Sl_wrDAck
PLB
O
0
Slave write data acknowledge
P33 Sl_wrComp
PLB
O
0
Slave write transfer complete
P34
Sl_rdDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
O
0
Slave read data bus
P35 Sl_rdDAck
PLB
O
0
Slave read data acknowledge
P36 Sl_rdComp
PLB
O
0
Slave read transfer complete
P37
Sl_MBusy[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave busy
P38
Sl_MWrErr[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave write error
P39
Sl_MRdErr[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave read error
Unused PLB Slave Interface Signals
P40 Sl_wrBTerm
PLB
O
0
Slave terminate write burst transfer
P41 Sl_rdWdAddr[0 : 3]
PLB
O
0
Slave read word address
P42 Sl_rdBTerm
PLB
O
0
Slave terminate read burst transfer
P43
Sl_MIRQ[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave interrupt request
Notes:
1. Please note that the SPI related port signals will be consumed internally and will not be available outside.
DS698 September 16, 2009
www.xilinx.com
7
Product Specification