DS698 Datasheet, PDF (18/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
The Interrupt controller has a register that can enable each interrupt independently. Bit assignment in
the Interrupt register for a 32-bit data bus is shown in Figure 11 and described in Table 14. The interrupt
register is a read/toggle on write register and by writing a ’1’ to a bit position within the register causes
the corresponding bit position in the register to ’toggle’. All register bits are cleared upon reset.
Figure Top x-ref 11
Reserved
DRR
Full
Tx FIFO
DTR
Half Empty
Empty MODF
0
24 25 26 27 28 29 30 31
DRR
Slave
Over-run
MODF
DTR
Under-run
DS698_11_072709
Figure 11: IP Interrupt Status Register (IPISR) (C_BASEADDR + 0x20)
Table 14: IP Interrupt Status Register (IPISR) Description (C_BASEADDR + 0x20)
Bit(s)
Name
0 - 24 Reserved
25 Tx FIFO Half Empty
26 DRR Over-run
27 DRR Full
Access
N/A
R/TOW⁽¹⁾
R/TOW⁽¹⁾
R/TOW⁽¹⁾
Reset
Value
N/A
’0’
’0’
’0’
Description
Reserved
Transmit FIFO Half Empty. IPISR bit(25) is the
transmit FIFO half empty interrupt. This bit is set by
a one-clock period strobe to the interrupt register
when the occupancy value is decremented from
"1000" to "0111". Note that "0111" means there
are 8 elements in the FIFO to be transmitted. This
interrupt exists only if the XPS InSystem Flash IP
Core is configured with FIFOs.
Data Receive Register/FIFO Over-run. IPISR
bit(26) is the data receive FIFO over-run interrupt.
This bit is set by a one-clock period strobe to the
interrupt register when an attempt to write data to
a full receive register or FIFO is made by the SPI
core logic in order to complete an SPI transfer. This
can occur when the SPI device is in master mode.
Data Receive Register/FIFO Full. IPISR bit(27) is
the data receive register full interrupt. Without
FIFOs, this bit is set at the end of an SPI element
(An element is a byte) transfer by a one-clock
period strobe to the interrupt register. With FIFOs,
this bit is set at the end of the SPI element transfer
when the receive FIFO has been filled by a
one-clock period strobe to the interrupt register.
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DS698 September 16, 2009
Product Specification