DS698 Datasheet, PDF (13/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
SPI Status Register (SPISR)
The SPI Status Register (SPISR) is a read-only register that gives the programmer visibility of the status
of some aspects of the XPS InSystem Flash IP Core. Internally this register is a part of XPS SPI IP Core.
The bit assignment in the SPISR is shown in Figure 4 and described in Table 7. Writing to the SPISR is
not recommended and if it is done by mistake, then no change will be there in register contents.
Figure Top x-ref 4
Reserved
Tx_Empty
MODF
Rx_Empty
0
26 27 28 29 30 31
Figure 4: SPI Status Register (C_BASEADDR + 0x64)
Rx_Full
Tx_Full
DS698_04_072709
Table 7: SPI Status Register (SPISR) Description (C_BASEADDR + 0x64)
Bit(s)
0 - 26
Name
Reserved
27 MODF
28 Tx_Full
29 Tx_Empty
30 Rx_Full
Core
Access
N/A
Read
Read
Read
Read
Reset
Value
N/A
’0’
’0’
’1’
’0’
Description
Reserved
Mode-Fault Error Flag. This flag is set if the SS signal goes
active while the SPI device is configured as a master. MODF
is automatically cleared by reading the SPISR. MODF does
generate an interrupt with a single cycle strobe when the
MODF bit transitions from a low to high.
’0’ = No error
’1’ = Error condition detected
As XPS InSystem Flash IP Core operates in the master SPI
mode only, this bit will always be ’0’.
Transmit Full. When a transmit FIFO exists, this bit will be set
high when the transmit FIFO is full.
When FIFOs don’t exist, this bit is set high when an PLB write
to the register has been made. This bit is cleared when the
SPI transfer is completed.
Transmit Empty. When a transmit FIFO exists, this bit will be
set high when the transmit FIFO is empty. The occupancy of
the FIFO is decremented with the completion of each SPI
transfer.
When FIFOs don’t exist, this bit is set with the completion of
an SPI transfer. Either with or without FIFOs, this bit is cleared
upon a PLB write to the FIFO or transmit register.
Receive Full. When a receive FIFO exists, this bit will be set
high when the receive FIFO is full. The occupancy of the FIFO
is incremented with the completion of each SPI transaction.
When FIFOs don’t exist, this bit is set high when an SPI
transfer has completed. Rx_Empty and Rx_Full are
complements in this case.
DS698 September 16, 2009
www.xilinx.com
13
Product Specification