DS698 Datasheet, PDF (19/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Table 14: IP Interrupt Status Register (IPISR) Description (C_BASEADDR + 0x20) (Contd)
Bit(s)
Name
Access
Reset
Value
Description
28 DTR Under-run
R/TOW⁽¹⁾
Data Transmit Register/FIFO Under-run. IPISR
bit(28) is the data transmit register/FIFO under-run
interrupt. This bit is set at the end of an SPI
element transfer by a one-clock period strobe to
’0’ the interrupt register when data is requested from
an "empty" transmit register/FIFO by the SPI core
logic in order to perform an SPI transfer.
As XPS InSystem Flash IP Core operates in the
master SPI mode only, this bit will always be ’0’.
29 DTR Empty
R/TOW⁽¹⁾
Data Transmit Register/FIFO Empty. IPISR
bit(29) is the data transmit register/FIFO empty
interrupt. Without FIFOs, this bit is set at the end of
an SPI element transfer by a one-clock period
strobe to the interrupt register. With FIFOs, this bit
is set at the end of the SPI element transfer when
’0’
the transmit FIFO is emptied by a one-clock period
strobe to the interrupt register. In the context of the
M68HC11 reference manual, when configured
without FIFOs, this interrupt is equivalent in
information content to the complement of SPI
transfer complete flag (SPIF) interrupt bit.
In master mode if this bit is set to ’1’ no more SPI
transfers are permitted.
30 Slave MODF
R/TOW⁽¹⁾
Slave Mode-Fault Error. IPISR bit(30) is the slave
mode-fault error flag. This interrupt is generated if
the SS signal goes active while the SPI device is
configured as a slave but is not enabled. This bit is
set immediately upon SS going active and
’0’
continually set if SS is active and the device is not
enabled.
Note: As XPS InSystem Flash IP Core operates in
the master SPI mode only, this bit will always be
set to ’0’.
31 MODF
R/TOW⁽¹⁾
Mode-Fault Error. IPISR bit(31) is the mode-fault
error flag. This interrupt is generated if the SS
signal goes active while the SPI device is
configured as a master. This bit is set immediately
’0’
upon SS going active.
Note: As XPS InSystem Flash IP Core operates in
the master SPI mode only, this bit will always be
set to ’0’.
Notes:
1. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position
in the register to toggle.
DS698 September 16, 2009
www.xilinx.com
19
Product Specification