DS698 Datasheet, PDF (4/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
(CPHA = 1 and CPOL = 1) and it communicates using 8-bit mode. Please read the XPS InSystem Flash
IP Core Parameter - Port Dependencies section carefully.
XPS InSystem Flash IP Core Design Parameters
To allow the user to obtain a XPS InSystem Flash IP Core that is uniquely tailored for the system, certain
features can be parameterized. Parameterization affords a measure of control over the function,
resource usage, and performance of the actually implemented XPS InSystem Flash IP Core. The
features that can be parameterized are as shown in Table 1.
Table 1: XPS InSystem Flash IP Core Design Parameters
Generic Feature/Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
System Parameters
G1 Target FPGA family
C_FAMILY⁽¹⁾
"spartan3a"
"spartan3a" string
PLB Parameters
G2 PLB base address
C_BASEADDR
Valid Address⁽²⁾
None⁽³⁾
std_logic
_vector
G3 PLB high address
C_HIGHADDR
Valid Address⁽²⁾
None⁽³⁾
std_logic
_vector
G4
PLB least significant
address bus width
C_SPLB_AWIDTH
32
32
integer
G5 PLB data width
C_SPLB_DWIDTH
32, 64, 128
32
integer
G6 Shared bus topology
C_SPLB_P2P
0 = Shared bus
topology⁽⁴⁾
0
integer
G7
PLB master ID bus
Width
C_SPLB_MID_
WIDTH
log₂(C_SPLB_
NU_MASTERS) with
1
a minimum value of 1
integer
G8
Number of PLB masters
C_SPLB_NUM_
MASTERS
1 - 16
1
integer
G9
Width of the slave data C_SPLB_NATIVE_
bus
DWIDTH
32
32
integer
G10 Burst support
C_SPLB_
0 = No burst
SUPPORT_BURSTS support⁽⁵⁾
0
integer
XPS InSystem Flash IP Core Parameters
G11
Include receive and
transmit FIFOs
C_FIFO_EXIST
0 = FIFOs not
included
1 = FIFOs included
1
integer
G12 SPI clock frequency ratio C_SCK_RATIO
2, 4, 16, 32, Nx16 for
N = 1, 2, 3,...,128
32
integer
G13
Total number of slave
select bits
C_NUM_SS_BITS
1⁽⁶⁾
1
integer
G14
Select number of
transfer bits as 8
C_NUM_
TRANSFER_BITS
8⁽⁶⁾
8
integer
4
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DS698 September 16, 2009
Product Specification