DS698 Datasheet, PDF (25/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Device Utilization and Performance Benchmarks
Core Performance
Since the XPS InSystem Flash IP Core will be used with other design modules in the FPGA, the
utilization and timing numbers reported in this section are estimates only. When the XPS InSystem
Flash IP Core is combined with other designs in the system, the utilization of FPGA resources and
timing of the XPS InSystem Flash IP Core design will vary from the results reported here.
The XPS InSystem Flash IP Core resource utilization for various parameter combinations measured
with Spartan-3A as the target device are detailed in Table 16.
Table 16: Performance and Resource Utilization Benchmarks on the Spartan-3A FPGA
(xc3s700an-fgg484-4)
Parameter Values
(other parameters at default values)
Device Resources
Performance
Slices
Slice
Flip-
Flops
LUTs
F_MAX (MHz)
0
2
1
1
2
1
0
4
1
1
4
1
0
32
1
1
32
1
8
220
178
213
104
8
240
179
267
103
8
217
183
207
108
8
229
181
261
104
8
215
186
211
102
8
244
184
265
102
System Performance
To measure the system performance (F_MAX) of this core, this core was added to a Spartan-3A system as
the Device Under Test (DUT) as shown in Figure 14.
Because the XPS InSystem Flash IP Core will be used with other design modules in the FPGA, the
utilization and timing numbers reported in this section are estimates only. When this core is combined
with other designs in the system, the utilization of FPGA resources and timing of the core design will
vary from the results reported here.
DS698 September 16, 2009
www.xilinx.com
25
Product Specification