DS698 Datasheet, PDF (26/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Figure Top x-ref 1
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
MicroBlaze
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS698_14_072709
Figure 14: Spartan-3A FPGA System with the XPS InSystem Flash Core as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately
70% and the I/O utilization to approximately 80%. Using the default tool options and the slowest speed
grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 17.
Table 17: XPS InSystem Flash IP Core System Performance
Target FPGA
Target F_MAX (MHz)
S3A700an-4
90
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed
value across all systems.
Specification Exceptions
Exceptions from the Motorola M68HC11-Rev. 4.0 Reference Manual
All the design exceptions of XPS SPI IP Core will remain same for the XPS InSystem Flash IP Core as
well. For reference only, all the possible exceptions are listed here.
1. A slave mode-fault error interrupt is added to provide an interrupt if a SPI device is configured as
a slave and is selected when not enabled.
2. In this design, the SPIDTR and SPIDRR registers have independent addresses. This is an exception
to the M68HC11 specification which calls for two registers to have the same address.
3. All SS signals are required to be routed between SPI devices internally to the FPGA. This is because
toggling of the SS signal is utilized in slaves to minimize FPGA resources.
4. Manual control of the SS signals is provided by setting bit(24) in the SPICR register. When the
device is configured as a master and is enabled and bit(24) of the SPICR register is set, the vector in
the SPISSR register is asserted. When this mode is enabled, multiple elements can be transferred
without toggling the SS vector.
5. A control bit is provided to inhibit master transfers. This bit is effective in any master mode, but has
main utility in manual control of the SS signals.
6. In the M68HC11 implementation, the transmit register is transparent to the shift register which
necessitates the write collision error (WCOL) detection hardware. This is not implemented in this
design.
7. The interrupt enable bit (SPIE) defined by the M68HC11 specifications which resides in the
M68HC11 control register has been moved to the IPIER register. In the position of the SPIE bit, there
is a bit to select local master loopback mode for testing.
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DS698 September 16, 2009
Product Specification