DS698 Datasheet, PDF (10/27 Pages) Xilinx, Inc – XPS InSystem Flash

XPS InSystem Flash (v1.01b)
Details of XPS InSystem Flash IP Core Registers
The XPS InSystem Flash IP Core uses XPS SPI IP Core as base core. Therefore, all the XPS SPI IP Core
registers are listed and supported here. As the XPS SPI IP Core embedded in to XPS InSystem Flash and
must be configured in the SPI Master Mode only, as the XPS SPI IP Core must not be configured in slave
mode, some of the slave mode related register bits are non-applicable and must not be accessed while
writing the write-only or read-write registers. While reading those un-used slave register bits from the
read-only or read-write registers the particular slave operation related bit value should be either
ignored or should be left to default values. Please read the notes mentioned for such bits in register bit
description area.
Software Reset Register (SRR)
The Software Reset Register permits the programmer to reset the XPS InSystem Flash IP Core
independent of other devices in the system. To activate software generated reset, the value
0x0000_000A must be written to this register. Any other write access generates an error condition with
undefined results and generates an error. The bit assignment in the software reset register is shown in
Figure 2 and described in Table 5. The effect of an attempt to read this register is undefined.
Figure Top x-ref 2
0
31
Reset
Figure 2: Software Reset Register (C_BASEADDR + 0x40)
DS698_01_072709
Table 5: Software Reset Register (SRR) Description (C_BASEADDR + 0x40)
Bit(s)
Name
Core
Access
0 - 31 Reset Write only
Reset
Value
N/A
Description
The only allowed operation on this register is a write of
0x0000000A, which resets the XPS InSystem Flash IP Core. Read
is not recommended.
After reset all the internal registers of the XPS SPI IP Core will be initialized to their own default values.
SPI Control Register (SPICR)
The SPI Control Register (SPICR) gives the programmer control over various aspects of the IP Core. The
bit assignment in the SPICR is shown in Figure 3 and described in Table 6. While accessing ISF, please
make sure that the XPS SPI IP Core is always configured in master mode only. The ISF supports the SPI
Mode-3 transfer protocol, so care should be taken while initializing the SPI Control Register. It’s bit-27
(CPHA) and bit-28 (CPOL) must always be written with ’1’ to support SPI Mode-3 protocol.
10
www.xilinx.com
DS698 September 16, 2009
Product Specification