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DS680 Datasheet, PDF (9/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs
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Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Table 15: Processor Block Switching Characteristics
Description
Setup and Hold Relative to Clock (CPMC405CLOCK)
Clock and Power Management control inputs
Reset control inputs
Debug control inputs
Trace control inputs
External Interrupt Controller control inputs
Clock to Out
Clock and Power Management control outputs
Reset control outputs
Debug control outputs
Trace control outputs
Clock
CPMC405CLOCK minimum pulse width, High
CPMC405CLOCK minimum pulse width, Low
Table 16: Processor Block PLB Switching Characteristics
Description
Setup and Hold Relative to Clock (PLBCLK)
Processor Local Bus (ICU/DCU) control inputs
Processor Local Bus (ICU/DCU) data inputs
Clock to Out
Processor Local Bus (ICU/DCU) control outputs
Processor Local Bus (ICU/DCU) address bus outputs
Processor Local Bus (ICU/DCU) data bus outputs
Table 17: Processor Block JTAG Switching Characteristics
Description
Setup and Hold Relative to Clock (JTAGC405TCK)
JTAG control inputs
JTAG reset input
Clock to Out
JTAG control outputs
DS680 (v2.0) April 12, 2010
Product Specification
www.xilinx.com
Symbol
TPPCDCK_CORECKI
TPPCCKD_CORECKI
TPPCDCK_RSTCHIP
TPPCCKD_RSTCHIP
TPPCDCK_EXBUSHAK
TPPCCKD_EXBUSHAK
TPPCDCK_TRCDIS
TPPCCKD_TRCDIS
TPPCDCK_CINPIRQ
TPPCCKD_CINPIRQ
TPPCCKO_CORESLP
TPPCCKO_RSTCHIP
TPPCCKO_DBGLDAPU
TPPCCKO_TRCCYCLE
TCPWH
TCPWL
Symbol
TPPCDCK_ICUBUSY
TPPCCKD_ICUBUSY
TPPCDCK_ICURDDB
TPPCCKD_ICURDDB
TPPCCKO_DCUABORT
TPPCCKO_ICUABUS
TPPCCKO_DCUWRDBUS
Symbol
TPPCDCK_JTGTDI
TPPCCKD_JTGTDI
TPPCDCK_JTGTRSTN
TPPCCKD_JTGTRSTN
TPPCCKO_JTGTDO
Speed
Grade
-10
Units
0.74
0.23
ns Min
0.74
0.23
ns Min
0.74
0.23
ns Min
0.74
0.23
ns Min
1.40
0.23
ns Min
1.74
ns Max
1.83
ns Max
1.70
ns Max
1.83
ns Max
1.43
ns Min
1.43
ns Min
Speed
Grade
-10
Units
0.76
0.23
ns Min
1.15
0.23
ns Min
2.05
ns Max
2.13
ns Max
2.57
ns Max
Speed
Grade
-10
Units
1.48
0.23
ns Min
0.74
0.23
ns Min
2.14
ns Max
9