DS680 Datasheet, PDF (26/36 Pages) Xilinx, Inc – Space-Grade Virtex-4QV FPGAs

R
Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics
Table 37: Configuration Switching Characteristics (Cont’d)
Symbol
Description
Dynamic Reconfiguration Port (DRP) for DCM
CLKIN_FREQ_DLL_HF_MS_MAX Maximum frequency for DCLK
D_DCMADV_DADDR_DCLK_SETUP/
D_DCMADV_DADDR_DCLK_HOLD
DADDR setup/hold
D_DCMADV_DI_DCLK_SETUP/
D_DCMADV_DI_DCLK_HOLD
DI setup/hold
D_DCMADV_DEN_DCLK_SETUP/
D_DCMADV_DEN_DCLK_HOLD
DEN setup/hold time
D_DCMADV_DWE_DCLK_SETUP/
D_DCMADV_DWE_DCLK_HOLD
D_DCMADV_DCLK_DO
DWE setup/hold time
CLK to out of DO⁽¹⁾
D_DCMADV_DCLK_DRDY
CLK to out of DRDY
Notes:
1. DO holds until next DRP operation.
Speed Grade
Units
-10
400
0.72/0.00
MHz,
max
ns, max
0.72/0.00 ns, max
0.58/0.00 ns, max
0.58/0.00
0
0.92
ns, max
ns, max
ns, max
Master/Slave SelectMAP Parameters
Figure 1 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
Virtex-4 FPGA User Guide.
X-Ref Target - Figure 1
CCLK
CS_B
T_SMCSCC
T_SMCCCS
RDWR_B
DATA[0:7]
TSMCCW
T_SMDCC
BUSY
TSMCKBY
TSMCCD
T_SMWCC
No Write
Write
No Write
Write
Figure 1: SelectMAP Mode Data Loading Sequence (Generic)
DS680_01_032608
DS680 (v2.0) April 12, 2010
www.xilinx.com
Product Specification
26